nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: enhance class error debug info

Browse Source 
Updated gk20a_gr_handle_class_error with
sub channel info, mme related info.

Also printing the correct method info from
isr_data->offset by left shifting it by 2.

Generated following hw definitions for gk20a/gm20b/gp10b/gp106
to dump relevant data in gk20a_gr_handle_class_error:
gr_trapped_addr_mme_generated_v
gr_trapped_addr_datahigh_v
gr_trapped_addr_priv_v
gr_trapped_data_lo_r
gr_trapped_data_mme_r
gr_trapped_data_mme_pc_v

Bug 2003671

Change-Id: I02e15ef16d7498b6a7dc2af547a14e84d570e8a7
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574061
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2017-10-05 17:36:51 -07:00
committed by mobile promotions
parent 1760dc8e80
commit 9712b4e5ac
5 changed files with 114 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -5202,11 +5202,24 @@ static int gk20a_gr_handle_class_error(struct gk20a *g,
gr_class_error_code_v(gk20a_readl(g, gr_class_error_r()));
gk20a_gr_set_error_notifier(g, isr_data,
NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY);
nvgpu_err(g,
"class error 0x%08x, offset 0x%08x,"
" unhandled intr 0x%08x for channel %u",
isr_data->class_num, isr_data->offset,
gr_class_error, isr_data->chid);
nvgpu_err(g, "class error 0x%08x, offset 0x%08x,"
"sub channel 0x%08x mme generated %d,"
" mme pc 0x%08xdata high %d priv status %d"
" unhandled intr 0x%08x for channel %u",
isr_data->class_num, (isr_data->offset << 2),
gr_trapped_addr_subch_v(isr_data->addr),
gr_trapped_addr_mme_generated_v(isr_data->addr),
gr_trapped_data_mme_pc_v(
gk20a_readl(g, gr_trapped_data_mme_r())),
gr_trapped_addr_datahigh_v(isr_data->addr),
gr_trapped_addr_priv_v(isr_data->addr),
gr_class_error, isr_data->chid);
nvgpu_err(g, "trapped data low 0x%08x",
gk20a_readl(g, gr_trapped_data_lo_r()));
if (gr_trapped_addr_datahigh_v(isr_data->addr))
nvgpu_err(g, "trapped data high 0x%08x",
gk20a_readl(g, gr_trapped_data_hi_r()));
return -EINVAL;
}

24
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
View File

@@ -268,6 +268,22 @@ static inline u32 gr_trapped_addr_subch_v(u32 r)
{
return (r >> 16U) & 0x7U;
}
static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
{
return (r >> 20U) & 0x1U;
}
static inline u32 gr_trapped_addr_datahigh_v(u32 r)
{
return (r >> 24U) & 0x1U;
}
static inline u32 gr_trapped_addr_priv_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 gr_trapped_addr_status_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 gr_trapped_data_lo_r(void)
{
return 0x00400708U;
@@ -276,6 +292,14 @@ static inline u32 gr_trapped_data_hi_r(void)
{
return 0x0040070cU;
}
static inline u32 gr_trapped_data_mme_r(void)
{
return 0x00400710U;
}
static inline u32 gr_trapped_data_mme_pc_v(u32 r)
{
return (r >> 0U) & 0x7ffU;
}
static inline u32 gr_status_r(void)
{
return 0x00400700U;

24
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
View File

@@ -256,6 +256,22 @@ static inline u32 gr_trapped_addr_subch_v(u32 r)
{
return (r >> 16U) & 0x7U;
}
static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
{
return (r >> 20U) & 0x1U;
}
static inline u32 gr_trapped_addr_datahigh_v(u32 r)
{
return (r >> 24U) & 0x1U;
}
static inline u32 gr_trapped_addr_priv_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 gr_trapped_addr_status_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 gr_trapped_data_lo_r(void)
{
return 0x00400708U;
@@ -264,6 +280,14 @@ static inline u32 gr_trapped_data_hi_r(void)
{
return 0x0040070cU;
}
static inline u32 gr_trapped_data_mme_r(void)
{
return 0x00400710U;
}
static inline u32 gr_trapped_data_mme_pc_v(u32 r)
{
return (r >> 0U) & 0x7ffU;
}
static inline u32 gr_status_r(void)
{
return 0x00400700U;

24
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
View File

@@ -252,6 +252,22 @@ static inline u32 gr_trapped_addr_subch_v(u32 r)
{
return (r >> 16U) & 0x7U;
}
static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
{
return (r >> 20U) & 0x1U;
}
static inline u32 gr_trapped_addr_datahigh_v(u32 r)
{
return (r >> 24U) & 0x1U;
}
static inline u32 gr_trapped_addr_priv_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 gr_trapped_addr_status_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 gr_trapped_data_lo_r(void)
{
return 0x00400708U;
@@ -260,6 +276,14 @@ static inline u32 gr_trapped_data_hi_r(void)
{
return 0x0040070cU;
}
static inline u32 gr_trapped_data_mme_r(void)
{
return 0x00400710U;
}
static inline u32 gr_trapped_data_mme_pc_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 gr_status_r(void)
{
return 0x00400700U;

24
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
View File

@@ -256,6 +256,22 @@ static inline u32 gr_trapped_addr_subch_v(u32 r)
{
return (r >> 16U) & 0x7U;
}
static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
{
return (r >> 20U) & 0x1U;
}
static inline u32 gr_trapped_addr_datahigh_v(u32 r)
{
return (r >> 24U) & 0x1U;
}
static inline u32 gr_trapped_addr_priv_v(u32 r)
{
return (r >> 28U) & 0x1U;
}
static inline u32 gr_trapped_addr_status_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 gr_trapped_data_lo_r(void)
{
return 0x00400708U;
@@ -264,6 +280,14 @@ static inline u32 gr_trapped_data_hi_r(void)
{
return 0x0040070cU;
}
static inline u32 gr_trapped_data_mme_r(void)
{
return 0x00400710U;
}
static inline u32 gr_trapped_data_mme_pc_v(u32 r)
{
return (r >> 0U) & 0xfffU;
}
static inline u32 gr_status_r(void)
{
return 0x00400700U;