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gpu: nvgpu: gsp: erase queue command for safety scheduler

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Changes:
- implemented erase queue command for safety scheduler to depopulate
control fifo parameters in safety scheduler FW.

NVGPU-9590
Bug 3935433

Change-Id: I2cd6cd967ac4dba61992dd285e45b18f34dda2ca
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2858533
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vivekku
2023-02-15 07:04:14 +00:00
committed by mobile promotions
parent a2a86eed27
commit 9773e7ca68
5 changed files with 30 additions and 1 deletions
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13
drivers/gpu/nvgpu/common/gsp_scheduler/gsp_ctrl_fifo.c
View File

@@ -96,4 +96,17 @@ int nvgpu_gsp_sched_send_queue_info(struct gk20a *g, struct nvgpu_nvs_ctrl_queue
exit:
return err;
}
int nvgpu_gsp_sched_erase_ctrl_fifo(struct gk20a *g)
{
int err = 0;
struct nv_flcn_cmd_gsp cmd = { };
err = gsp_send_cmd_and_wait_for_ack(g, &cmd, NV_GSP_UNIT_CONTROL_FIFO_ERASE, 0);
if (err != 0) {
nvgpu_err(g, "GSP ctrl fifo erase cmd failed");
}
return err;
};
#endif /* CONFIG_NVS_PRESENT*/

4
drivers/gpu/nvgpu/common/gsp_scheduler/gsp_runlist.c
View File

@@ -95,6 +95,10 @@ static void gsp_handle_cmd_ack(struct gk20a *g, struct nv_flcn_msg_gsp *msg,
nvgpu_gsp_dbg(g, "Reply to NV_GSP_UNIT_BIND_CTX_REG");
*command_ack = true;
break;
case NV_GSP_UNIT_CONTROL_FIFO_ERASE:
nvgpu_gsp_dbg(g, "Reply to NV_GSP_UNIT_CONTROL_FIFO_ERASE");
*command_ack = true;
break;
default:
nvgpu_err(g, "Un-handled response from GSP");
*command_ack = false;

3
drivers/gpu/nvgpu/common/gsp_scheduler/ipc/gsp_cmd.h
View File

@@ -50,7 +50,8 @@ struct gk20a;
#define NV_GSP_UNIT_QUERY_ACTIVE_DOMAIN 0X0CU
#define NV_GSP_UNIT_CONTROL_INFO_SEND 0X0DU
#define NV_GSP_UNIT_BIND_CTX_REG 0X0EU
#define NV_GSP_UNIT_END 0x0FU
#define NV_GSP_UNIT_CONTROL_FIFO_ERASE 0X0FU
#define NV_GSP_UNIT_END 0x10U
#define GSP_MSG_HDR_SIZE U32(sizeof(struct gsp_hdr))
#define GSP_CMD_HDR_SIZE U32(sizeof(struct gsp_hdr))

9
drivers/gpu/nvgpu/common/nvs/nvs_sched_ctrl.c
View File

@@ -29,6 +29,10 @@
#include <nvgpu/dma.h>
#include <nvgpu/runlist.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/enabled.h>
#if defined (CONFIG_NVS_PRESENT) && defined (CONFIG_NVGPU_GSP_SCHEDULER)
#include <nvgpu/gsp_sched.h>
#endif
/**
* @brief A structure for managing all the list of control-fifo users
@@ -614,6 +618,11 @@ void nvgpu_nvs_buffer_free(struct nvgpu_nvs_domain_ctrl_fifo *sched_ctrl,
#endif
if (nvgpu_mem_is_valid(&buf->mem)) {
#if defined (CONFIG_NVS_PRESENT) && defined (CONFIG_NVGPU_GSP_SCHEDULER)
if (nvgpu_is_enabled(g, (u32)(NVGPU_SUPPORT_GSP_SCHED))) {
nvgpu_gsp_sched_erase_ctrl_fifo(g);
}
#endif
nvgpu_dma_unmap_free(system_vm, &buf->mem);
}

2
drivers/gpu/nvgpu/include/nvgpu/gsp_sched.h
View File

@@ -131,5 +131,7 @@ bool nvgpu_gsp_is_ready(struct gk20a *g);
#ifdef CONFIG_NVS_PRESENT
int nvgpu_gsp_sched_send_queue_info(struct gk20a *g, struct nvgpu_nvs_ctrl_queue *queue,
enum nvgpu_nvs_ctrl_queue_direction queue_direction);
int nvgpu_gsp_sched_erase_ctrl_fifo(struct gk20a *g);
#endif
#endif /* GSP_SCHED_H */