nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: add fecs_host_int_enable hal

Browse Source 
This will be used to enable fecs interrupts per
chip.

Change-Id: Id99412ca1a9c4caad999c3458b0e9701515db4b9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642554
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2018-01-19 14:47:47 -08:00
committed by mobile promotions
parent 8e523a9a53
commit 9beefc4551
11 changed files with 52 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -441,6 +441,7 @@ struct gpu_ops {
u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g);
void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm,
struct nvgpu_gr_ctx *gr_ctx);
void (*fecs_host_int_enable)(struct gk20a *g);
} gr;
struct {
void (*init_hw)(struct gk20a *g);

27
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -4344,6 +4344,16 @@ void gr_gk20a_enable_hww_exceptions(struct gk20a *g)
gr_memfmt_hww_esr_reset_active_f());
}
void gr_gk20a_fecs_host_int_enable(struct gk20a *g)
{
gk20a_writel(g, gr_fecs_host_int_enable_r(),
gr_fecs_host_int_enable_ctxsw_intr1_enable_f() |
gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() |
gr_fecs_host_int_enable_umimp_firmware_method_enable_f() |
gr_fecs_host_int_enable_umimp_illegal_method_enable_f() |
gr_fecs_host_int_enable_watchdog_enable_f());
}
static int gk20a_init_gr_setup_hw(struct gk20a *g)
{
struct gr_gk20a *gr = &g->gr;
@@ -4407,12 +4417,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
gk20a_writel(g, gr_intr_en_r(), 0xFFFFFFFF);
/* enable fecs error interrupts */
gk20a_writel(g, gr_fecs_host_int_enable_r(),
gr_fecs_host_int_enable_ctxsw_intr1_enable_f() |
gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() |
gr_fecs_host_int_enable_umimp_firmware_method_enable_f() |
gr_fecs_host_int_enable_umimp_illegal_method_enable_f() |
gr_fecs_host_int_enable_watchdog_enable_f());
g->ops.gr.fecs_host_int_enable(g);
g->ops.gr.enable_hww_exceptions(g);
g->ops.gr.set_hww_esr_report_mask(g);
@@ -5124,15 +5129,9 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
int ret = 0;
gk20a_dbg_fn("");
if (!gr_fecs_intr)
return 0;
nvgpu_err(g,
"unhandled fecs error interrupt 0x%08x for channel %u",
gr_fecs_intr, isr_data->chid);
if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) {
gk20a_gr_set_error_notifier(g, isr_data,
NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD);
@@ -5141,6 +5140,10 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)),
isr_data->data_lo);
ret = -1;
} else {
nvgpu_err(g,
"fecs error interrupt 0x%08x for channel %u",
gr_fecs_intr, isr_data->chid);
}
gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -732,7 +732,7 @@ static inline void gr_gk20a_free_cyclestats_snapshot_data(struct gk20a *g)
}
#endif
void gr_gk20a_fecs_host_int_enable(struct gk20a *g);
int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
struct gr_gk20a_isr_data *isr_data);
int gk20a_gr_lock_down_sm(struct gk20a *g,

1
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -310,6 +310,7 @@ static const struct gpu_ops gm20b_ops = {
.get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
.disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
.init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data,
.fecs_host_int_enable = gr_gk20a_fecs_host_int_enable,
},
.fb = {
.reset = fb_gk20a_reset,

3
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -371,7 +371,8 @@ static const struct gpu_ops gp106_ops = {
.set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
.create_gr_sysfs = NULL,
.set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode,
.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode
.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode,
.fecs_host_int_enable = gr_gk20a_fecs_host_int_enable,
},
.fb = {
.reset = gp106_fb_reset,

1
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -340,6 +340,7 @@ static const struct gpu_ops gp10b_ops = {
.get_max_gfxp_wfi_timeout_count =
gr_gp10b_get_max_gfxp_wfi_timeout_count,
.dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats,
.fecs_host_int_enable = gr_gk20a_fecs_host_int_enable,
},
.fb = {
.reset = fb_gk20a_reset,

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -425,6 +425,7 @@ static const struct gpu_ops gv100_ops = {
.handle_tpc_sm_ecc_exception =
gr_gv11b_handle_tpc_sm_ecc_exception,
.decode_egpc_addr = gv11b_gr_decode_egpc_addr,
.fecs_host_int_enable = gr_gv11b_fecs_host_int_enable,
},
.fb = {
.reset = gv100_fb_reset,

19
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -321,6 +321,19 @@ void gr_gv11b_enable_hww_exceptions(struct gk20a *g)
gr_memfmt_hww_esr_reset_active_f());
}
void gr_gv11b_fecs_host_int_enable(struct gk20a *g)
{
gk20a_writel(g, gr_fecs_host_int_enable_r(),
gr_fecs_host_int_enable_ctxsw_intr1_enable_f() |
gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() |
gr_fecs_host_int_enable_umimp_firmware_method_enable_f() |
gr_fecs_host_int_enable_umimp_illegal_method_enable_f() |
gr_fecs_host_int_enable_watchdog_enable_f() |
gr_fecs_host_int_enable_flush_when_busy_enable_f() |
gr_fecs_host_int_enable_ecc_corrected_enable_f() |
gr_fecs_host_int_enable_ecc_uncorrected_enable_f());
}
void gr_gv11b_enable_exceptions(struct gk20a *g)
{
struct gr_gk20a *gr = &g->gr;
@@ -2249,13 +2262,13 @@ int gr_gv11b_handle_fecs_error(struct gk20a *g,
u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
int ret;
gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "");
ret = gr_gp10b_handle_fecs_error(g, __ch, isr_data);
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " ");
/* Handle ECC errors */
gr_gv11b_handle_fecs_ecc_error(g, gr_fecs_intr);
ret = gr_gp10b_handle_fecs_error(g, __ch, isr_data);
return ret;
}

1
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -133,6 +133,7 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
bool sm_debugger_attached, struct channel_gk20a *fault_ch,
bool *early_exit, bool *ignore_debugger);
void gr_gv11b_fecs_host_int_enable(struct gk20a *g);
int gr_gv11b_handle_fecs_error(struct gk20a *g,
struct channel_gk20a *__ch,
struct gr_gk20a_isr_data *isr_data);

1
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -398,6 +398,7 @@ static const struct gpu_ops gv11b_ops = {
gr_gv11b_get_max_gfxp_wfi_timeout_count,
.ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg,
.dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats,
.fecs_host_int_enable = gr_gv11b_fecs_host_int_enable,
},
.fb = {
.reset = gv11b_fb_reset,

12
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
View File

@@ -1988,6 +1988,18 @@ static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
{
return 0x80000U;
}
static inline u32 gr_fecs_host_int_enable_flush_when_busy_enable_f(void)
{
return 0x100000U;
}
static inline u32 gr_fecs_host_int_enable_ecc_corrected_enable_f(void)
{
return 0x200000U;
}
static inline u32 gr_fecs_host_int_enable_ecc_uncorrected_enable_f(void)
{
return 0x400000U;
}
static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
{
return 0x00409614U;