nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Sync kernel headers with generator tool

Browse Source 
HW headers in nvgpu have gotten a bit out of date. Regenerate
headers and add the following registers:

* Add PTIMER timeout registers to all chips
* Add PD, SCC, SSYNC and MME interrupt registers to all chips
* Add HWW ESR INFO register to all chips

Change-Id: I34e09371083ac1568666b0cd487a106fad56aa12
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807709
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-08-27 13:58:41 -07:00
committed by mobile promotions
parent 220c10fac4
commit 9c60230b57
7 changed files with 127 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -98,15 +98,15 @@ static inline u32 timer_pri_timeout_save_0_r(void)
}
static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
{
return (r >> 31) & 0x1;
return (r >> 31U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
{
return (r >> 2) & 0x3fffff;
return (r >> 2U) & 0x3fffffU;
}
static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
{
return (r >> 1) & 0x1;
return (r >> 1U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_1_r(void)
{

24
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
View File

@@ -184,6 +184,22 @@ static inline u32 gr_exception_sked_m(void)
{
return 0x1U << 8U;
}
static inline u32 gr_exception_pd_m(void)
{
return 0x1U << 2U;
}
static inline u32 gr_exception_scc_m(void)
{
return 0x1U << 3U;
}
static inline u32 gr_exception_ssync_m(void)
{
return 0x1U << 5U;
}
static inline u32 gr_exception_mme_m(void)
{
return 0x1U << 7U;
}
static inline u32 gr_exception1_r(void)
{
return 0x00400118U;
@@ -544,6 +560,10 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void)
{
return 0x80000000U;
}
static inline u32 gr_fe_hww_esr_info_r(void)
{
return 0x004041b0U;
}
static inline u32 gr_fe_go_idle_timeout_r(void)
{
return 0x00404154U;
@@ -596,6 +616,10 @@ static inline u32 gr_mme_hww_esr_en_enable_f(void)
{
return 0x80000000U;
}
static inline u32 gr_mme_hww_esr_info_r(void)
{
return 0x00404494U;
}
static inline u32 gr_memfmt_hww_esr_r(void)
{
return 0x00404600U;

14
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -96,6 +96,18 @@ static inline u32 timer_pri_timeout_save_0_r(void)
{
return 0x00009084U;
}
static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
{
return (r >> 2U) & 0x3fffffU;
}
static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_1_r(void)
{
return 0x00009088U;

28
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
View File

@@ -180,6 +180,26 @@ static inline u32 gr_exception_ds_m(void)
{
return 0x1U << 4U;
}
static inline u32 gr_exception_sked_m(void)
{
return 0x1U << 8U;
}
static inline u32 gr_exception_pd_m(void)
{
return 0x1U << 2U;
}
static inline u32 gr_exception_scc_m(void)
{
return 0x1U << 3U;
}
static inline u32 gr_exception_ssync_m(void)
{
return 0x1U << 5U;
}
static inline u32 gr_exception_mme_m(void)
{
return 0x1U << 7U;
}
static inline u32 gr_exception1_r(void)
{
return 0x00400118U;
@@ -672,6 +692,10 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void)
{
return 0x80000000U;
}
static inline u32 gr_fe_hww_esr_info_r(void)
{
return 0x004041b0U;
}
static inline u32 gr_fe_go_idle_timeout_r(void)
{
return 0x00404154U;
@@ -724,6 +748,10 @@ static inline u32 gr_mme_hww_esr_en_enable_f(void)
{
return 0x80000000U;
}
static inline u32 gr_mme_hww_esr_info_r(void)
{
return 0x00404494U;
}
static inline u32 gr_memfmt_hww_esr_r(void)
{
return 0x00404600U;

22
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -124,6 +124,26 @@ static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
{
return 0x20U;
}
static inline u32 ram_in_use_ver2_pt_format_f(u32 v)
{
return (v & 0x1U) << 10U;
}
static inline u32 ram_in_use_ver2_pt_format_m(void)
{
return 0x1U << 10U;
}
static inline u32 ram_in_use_ver2_pt_format_w(void)
{
return 128U;
}
static inline u32 ram_in_use_ver2_pt_format_true_f(void)
{
return 0x400U;
}
static inline u32 ram_in_use_ver2_pt_format_false_f(void)
{
return 0x0U;
}
static inline u32 ram_in_big_page_size_f(u32 v)
{
return (v & 0x1U) << 11U;

24
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
View File

@@ -184,6 +184,22 @@ static inline u32 gr_exception_sked_m(void)
{
return 0x1U << 8U;
}
static inline u32 gr_exception_pd_m(void)
{
return 0x1U << 2U;
}
static inline u32 gr_exception_scc_m(void)
{
return 0x1U << 3U;
}
static inline u32 gr_exception_ssync_m(void)
{
return 0x1U << 5U;
}
static inline u32 gr_exception_mme_m(void)
{
return 0x1U << 7U;
}
static inline u32 gr_exception1_r(void)
{
return 0x00400118U;
@@ -724,6 +740,10 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void)
{
return 0x80000000U;
}
static inline u32 gr_fe_hww_esr_info_r(void)
{
return 0x004041b0U;
}
static inline u32 gr_fe_go_idle_timeout_r(void)
{
return 0x00404154U;
@@ -776,6 +796,10 @@ static inline u32 gr_mme_hww_esr_en_enable_f(void)
{
return 0x80000000U;
}
static inline u32 gr_mme_hww_esr_info_r(void)
{
return 0x00404494U;
}
static inline u32 gr_memfmt_hww_esr_r(void)
{
return 0x00404600U;

14
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -96,6 +96,18 @@ static inline u32 timer_pri_timeout_save_0_r(void)
{
return 0x00009084U;
}
static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
{
return (r >> 31U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
{
return (r >> 2U) & 0x3fffffU;
}
static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
{
return (r >> 1U) & 0x1U;
}
static inline u32 timer_pri_timeout_save_1_r(void)
{
return 0x00009088U;