gpu: nvgpu: add HAL to update doorbell

Add new HAL gops.fifo.ring_channel_doorbell() to update channel doorbell
register and to trigger a runlist scan

Set existing API gv11b_ring_channel_doorbell() to this HAL for all volta chips

Jira NVGPUT-18

Change-Id: I9d5e84cf5aa7b763363d84befe169efda00a0932
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702114
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -672,6 +672,7 @@ struct gpu_ops {
 		void (*runlist_hw_submit)(struct gk20a *g, u32 runlist_id,
 			u32 count, u32 buffer_index);
 		int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id);
+		void (*ring_channel_doorbell)(struct channel_gk20a *c);
 	} fifo;
 	struct pmu_v {
 		u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -587,6 +587,7 @@ static const struct gpu_ops gv100_ops = {
 		.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
 		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
 		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
+		.ring_channel_doorbell = gv11b_ring_channel_doorbell,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gv100_get_netlist_name,

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -209,7 +209,7 @@ int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
 }
 
 
-static void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
+void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
 {
 	struct fifo_gk20a *f = &c->g->fifo;
 	u32 hw_chid = f->channel_base + c->chid;
@@ -249,7 +249,7 @@ void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c)
 	/* Commit everything to GPU. */
 	nvgpu_mb();
 
-	gv11b_ring_channel_doorbell(c);
+	g->ops.fifo.ring_channel_doorbell(c);
 }
 
 void channel_gv11b_unbind(struct channel_gk20a *ch)

drivers/gpu/nvgpu/gv11b/fifo_gv11b.h

@@ -123,4 +123,5 @@ u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g);
 void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g,
 			struct channel_gk20a *ch, struct nvgpu_mem *mem);
 void gv11b_userd_writeback_config(struct gk20a *g);
+void gv11b_ring_channel_doorbell(struct channel_gk20a *c);
 #endif

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -560,6 +560,7 @@ static const struct gpu_ops gv11b_ops = {
 		.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
 		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
 		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
+		.ring_channel_doorbell = gv11b_ring_channel_doorbell,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gv11b_get_netlist_name,

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -421,6 +421,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
 		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
 		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
+		.ring_channel_doorbell = gv11b_ring_channel_doorbell,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gv11b_get_netlist_name,