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gpu: nvgpu: Move Intr handling common code to CIC

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CIC (Central Interrupt controller) will be responsible for the
interrupt handling. common.cic unit is the placeholder for all
interrupt related code. Move interrupt related defines and
Public APIs present in common.mc to common.cic.
Note: The common.mc interrupts related struct definitions are
not moved as part of this patch.

Adapt the code to use interrupt handling related defines and public
APIs migrated from common.mc to common.cic

JIRA NVGPU-6899

Change-Id: I747e2b556c0dd66d58d74ee5bb36768b9370d276
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2535618
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2021-05-25 11:08:28 +00:00
committed by mobile promotions
parent 9034b1676e
commit 9f43914933
42 changed files with 726 additions and 695 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/nvgpu-common.yaml
View File

@@ -136,7 +136,6 @@ mc:
safe: yes
owner: Seema K
sources: [ common/mc/mc.c,
common/mc/mc_intr.c,
include/nvgpu/mc.h,
include/nvgpu/gops/mc.h ]
class:
@@ -1055,6 +1054,7 @@ cic:
owner: Tejal K
safe: yes
sources: [ common/cic/cic.c,
common/cic/cic_intr.c,
common/cic/ce_cic.c,
common/cic/ctxsw_cic.c,
common/cic/msg_cic.c,

2
drivers/gpu/nvgpu/Makefile
View File

@@ -210,7 +210,6 @@ nvgpu-y += \
common/perf/perfbuf.o \
common/therm/therm.o \
common/mc/mc.o \
common/mc/mc_intr.o \
common/sync/channel_sync.o \
common/sync/channel_sync_semaphore.o \
common/semaphore/semaphore_sea.o \
@@ -310,6 +309,7 @@ nvgpu-y += \
common/rc/rc.o \
common/grmgr/grmgr.o \
common/cic/cic.o \
common/cic/cic_intr.o \
common/cic/ce_cic.o \
common/cic/ctxsw_cic.o \
common/cic/ecc_cic.o \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -148,11 +148,11 @@ srcs += common/device.c \
common/fifo/engines.c \
common/fifo/pbdma_status.c \
common/mc/mc.c \
common/mc/mc_intr.c \
common/rc/rc.c \
common/ce/ce.c \
common/grmgr/grmgr.c \
common/cic/cic.c \
common/cic/cic_intr.c \
common/cic/ce_cic.c \
common/cic/ctxsw_cic.c \
common/cic/ecc_cic.c \

5
drivers/gpu/nvgpu/common/ce/ce.c
View File

@@ -26,6 +26,7 @@
#include <nvgpu/device.h>
#include <nvgpu/ce.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/cic.h>
#include <nvgpu/mc.h>
int nvgpu_ce_init_support(struct gk20a *g)
@@ -63,8 +64,8 @@ int nvgpu_ce_init_support(struct gk20a *g)
}
/** Enable interrupts at MC level */
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_CE, MC_INTR_ENABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_CE, MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE);
return 0;
}

74
drivers/gpu/nvgpu/common/mc/mc_intr.c → drivers/gpu/nvgpu/common/cic/cic_intr.c
View File

@@ -1,7 +1,5 @@
/*
* GK20A Master Interrupt Control
*
* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,13 +20,13 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/trace.h>
int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout)
int nvgpu_cic_wait_for_stall_interrupts(struct gk20a *g, u32 timeout)
{
/* wait until all stalling irqs are handled */
return NVGPU_COND_WAIT(&g->mc.sw_irq_stall_last_handled_cond,
@@ -36,7 +34,7 @@ int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout)
timeout);
}
int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout)
int nvgpu_cic_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout)
{
/* wait until all non-stalling irqs are handled */
return NVGPU_COND_WAIT(&g->mc.sw_irq_nonstall_last_handled_cond,
@@ -44,22 +42,22 @@ int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout)
timeout);
}
void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
void nvgpu_cic_wait_for_deferred_interrupts(struct gk20a *g)
{
int ret;
ret = nvgpu_wait_for_stall_interrupts(g, 0U);
ret = nvgpu_cic_wait_for_stall_interrupts(g, 0U);
if (ret != 0) {
nvgpu_err(g, "wait for stall interrupts failed %d", ret);
}
ret = nvgpu_wait_for_nonstall_interrupts(g, 0U);
ret = nvgpu_cic_wait_for_nonstall_interrupts(g, 0U);
if (ret != 0) {
nvgpu_err(g, "wait for nonstall interrupts failed %d", ret);
}
}
void nvgpu_mc_intr_mask(struct gk20a *g)
void nvgpu_cic_intr_mask(struct gk20a *g)
{
unsigned long flags = 0;
@@ -71,14 +69,14 @@ void nvgpu_mc_intr_mask(struct gk20a *g)
}
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_mc_log_pending_intrs(struct gk20a *g)
void nvgpu_cic_log_pending_intrs(struct gk20a *g)
{
if (g->ops.mc.log_pending_intrs != NULL) {
g->ops.mc.log_pending_intrs(g);
}
}
void nvgpu_mc_intr_enable(struct gk20a *g)
void nvgpu_cic_intr_enable(struct gk20a *g)
{
unsigned long flags = 0;
@@ -90,7 +88,7 @@ void nvgpu_mc_intr_enable(struct gk20a *g)
}
#endif
void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
void nvgpu_cic_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
{
unsigned long flags = 0;
@@ -99,7 +97,7 @@ void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_mc_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
void nvgpu_cic_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
{
unsigned long flags = 0;
@@ -108,7 +106,7 @@ void nvgpu_mc_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_mc_intr_stall_pause(struct gk20a *g)
void nvgpu_cic_intr_stall_pause(struct gk20a *g)
{
unsigned long flags = 0;
@@ -117,7 +115,7 @@ void nvgpu_mc_intr_stall_pause(struct gk20a *g)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_mc_intr_stall_resume(struct gk20a *g)
void nvgpu_cic_intr_stall_resume(struct gk20a *g)
{
unsigned long flags = 0;
@@ -126,7 +124,7 @@ void nvgpu_mc_intr_stall_resume(struct gk20a *g)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_mc_intr_nonstall_pause(struct gk20a *g)
void nvgpu_cic_intr_nonstall_pause(struct gk20a *g)
{
unsigned long flags = 0;
@@ -135,7 +133,7 @@ void nvgpu_mc_intr_nonstall_pause(struct gk20a *g)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
void nvgpu_mc_intr_nonstall_resume(struct gk20a *g)
void nvgpu_cic_intr_nonstall_resume(struct gk20a *g)
{
unsigned long flags = 0;
@@ -144,14 +142,14 @@ void nvgpu_mc_intr_nonstall_resume(struct gk20a *g)
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
static void nvgpu_intr_nonstall_work(struct gk20a *g, u32 work_ops)
static void nvgpu_cic_intr_nonstall_work(struct gk20a *g, u32 work_ops)
{
bool semaphore_wakeup, post_events;
semaphore_wakeup =
(((work_ops & NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ?
(((work_ops & NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ?
true : false);
post_events = (((work_ops & NVGPU_NONSTALL_OPS_POST_EVENTS) != 0U) ?
post_events = (((work_ops & NVGPU_CIC_NONSTALL_OPS_POST_EVENTS) != 0U) ?
true : false);
if (semaphore_wakeup) {
@@ -159,43 +157,43 @@ static void nvgpu_intr_nonstall_work(struct gk20a *g, u32 work_ops)
}
}
u32 nvgpu_intr_nonstall_isr(struct gk20a *g)
u32 nvgpu_cic_intr_nonstall_isr(struct gk20a *g)
{
u32 non_stall_intr_val = 0U;
if (nvgpu_is_powered_off(g)) {
return NVGPU_INTR_UNMASK;
return NVGPU_CIC_INTR_UNMASK;
}
/* not from gpu when sharing irq with others */
non_stall_intr_val = g->ops.mc.intr_nonstall(g);
if (non_stall_intr_val == 0U) {
return NVGPU_INTR_NONE;
return NVGPU_CIC_INTR_NONE;
}
nvgpu_mc_intr_nonstall_pause(g);
nvgpu_cic_intr_nonstall_pause(g);
if (g->sw_quiesce_pending) {
return NVGPU_INTR_QUIESCE_PENDING;
return NVGPU_CIC_INTR_QUIESCE_PENDING;
}
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 1);
return NVGPU_INTR_HANDLE;
return NVGPU_CIC_INTR_HANDLE;
}
void nvgpu_intr_nonstall_handle(struct gk20a *g)
void nvgpu_cic_intr_nonstall_handle(struct gk20a *g)
{
int err;
u32 nonstall_ops = 0;
nonstall_ops = g->ops.mc.isr_nonstall(g);
if (nonstall_ops != 0U) {
nvgpu_intr_nonstall_work(g, nonstall_ops);
nvgpu_cic_intr_nonstall_work(g, nonstall_ops);
}
/* sync handled irq counter before re-enabling interrupts */
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 0);
nvgpu_mc_intr_nonstall_resume(g);
nvgpu_cic_intr_nonstall_resume(g);
err = nvgpu_cond_broadcast(&g->mc.sw_irq_nonstall_last_handled_cond);
if (err != 0) {
@@ -203,36 +201,36 @@ void nvgpu_intr_nonstall_handle(struct gk20a *g)
}
}
u32 nvgpu_intr_stall_isr(struct gk20a *g)
u32 nvgpu_cic_intr_stall_isr(struct gk20a *g)
{
u32 mc_intr_0 = 0U;
nvgpu_trace_intr_stall_start(g);
if (nvgpu_is_powered_off(g)) {
return NVGPU_INTR_UNMASK;
return NVGPU_CIC_INTR_UNMASK;
}
/* not from gpu when sharing irq with others */
mc_intr_0 = g->ops.mc.intr_stall(g);
if (mc_intr_0 == 0U) {
return NVGPU_INTR_NONE;
return NVGPU_CIC_INTR_NONE;
}
nvgpu_mc_intr_stall_pause(g);
nvgpu_cic_intr_stall_pause(g);
if (g->sw_quiesce_pending) {
return NVGPU_INTR_QUIESCE_PENDING;
return NVGPU_CIC_INTR_QUIESCE_PENDING;
}
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 1);
nvgpu_trace_intr_stall_done(g);
return NVGPU_INTR_HANDLE;
return NVGPU_CIC_INTR_HANDLE;
}
void nvgpu_intr_stall_handle(struct gk20a *g)
void nvgpu_cic_intr_stall_handle(struct gk20a *g)
{
int err;
@@ -244,7 +242,7 @@ void nvgpu_intr_stall_handle(struct gk20a *g)
/* sync handled irq counter before re-enabling interrupts */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 0);
nvgpu_mc_intr_stall_resume(g);
nvgpu_cic_intr_stall_resume(g);
err = nvgpu_cond_broadcast(&g->mc.sw_irq_stall_last_handled_cond);
if (err != 0) {

5
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -45,6 +45,7 @@
#include <nvgpu/ptimer.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/engines.h>
#include <nvgpu/channel.h>
@@ -958,7 +959,7 @@ static void channel_free(struct nvgpu_channel *ch, bool force)
/* wait until all pending interrupts for recently completed
* jobs are handled */
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
/* prevent new refs */
nvgpu_spinlock_acquire(&ch->ref_obtain_lock);
@@ -1015,7 +1016,7 @@ static void channel_free(struct nvgpu_channel *ch, bool force)
/* make sure we don't have deferred interrupts pending that
* could still touch the channel */
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
unbind:
g->ops.channel.unbind(ch);

13
drivers/gpu/nvgpu/common/fifo/fifo.c
View File

@@ -1,7 +1,7 @@
/*
* FIFO
*
* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -34,6 +34,7 @@
#include <nvgpu/tsg.h>
#include <nvgpu/vm_area.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/mc.h>
#include <nvgpu/swprofile.h>
#include <nvgpu/fifo/swprofile.h>
@@ -280,12 +281,12 @@ static void disable_fifo_interrupts(struct gk20a *g)
g->ops.fifo.intr_1_enable(g, false);
if (g->ops.fifo.intr_top_enable == NULL) {
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_FIFO,
MC_INTR_DISABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_FIFO,
MC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_DISABLE);
} else {
g->ops.fifo.intr_top_enable(g, MC_INTR_DISABLE);
g->ops.fifo.intr_top_enable(g, NVGPU_CIC_INTR_DISABLE);
}
}

3
drivers/gpu/nvgpu/common/fifo/preempt.c
View File

@@ -29,6 +29,7 @@
#include <nvgpu/tsg.h>
#include <nvgpu/preempt.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/rc.h>
#ifdef CONFIG_NVGPU_LS_PMU
#include <nvgpu/pmu/mutex.h>
@@ -102,7 +103,7 @@ int nvgpu_fifo_preempt_tsg(struct gk20a *g, struct nvgpu_tsg *tsg)
break;
}
ret = nvgpu_wait_for_stall_interrupts(g, preempt_retry_timeout);
ret = nvgpu_cic_wait_for_stall_interrupts(g, preempt_retry_timeout);
if (ret != 0) {
nvgpu_log_info(g, "wait for stall interrupts failed %d", ret);
}

17
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -45,6 +45,7 @@
#include <nvgpu/power_features/cg.h>
#include <nvgpu/power_features/pg.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/device.h>
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu/engines.h>
@@ -188,10 +189,10 @@ static void disable_gr_interrupts(struct gk20a *g)
g->ops.gr.intr.enable_exceptions(g, g->gr->config, false);
/** Disable interrupts at MC level */
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_GR,
MC_INTR_DISABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_GR,
MC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR,
NVGPU_CIC_INTR_DISABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR,
NVGPU_CIC_INTR_DISABLE);
}
int nvgpu_gr_suspend(struct gk20a *g)
@@ -592,8 +593,8 @@ static int gr_init_prepare_hw(struct gk20a *g)
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
/** Enable interrupts at MC level */
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_GR, MC_INTR_ENABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_GR, MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
return nvgpu_gr_exec_with_ret_for_each_instance(g,
gr_init_prepare_hw_impl(g));
@@ -710,8 +711,8 @@ static int nvgpu_gr_enable_hw_for_instance(struct gk20a *g)
nvgpu_cg_elcg_disable_no_wait(g);
/** Enable interrupts at MC level */
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_GR, MC_INTR_ENABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_GR, MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE);
err = gr_init_prepare_hw_impl(g);
if (err != 0) {

8
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -73,9 +73,9 @@ void nvgpu_check_gpu_state(struct gk20a *g)
static void gk20a_mask_interrupts(struct gk20a *g)
{
nvgpu_mc_intr_mask(g);
nvgpu_cic_intr_mask(g);
#ifdef CONFIG_NVGPU_NON_FUSA
nvgpu_mc_log_pending_intrs(g);
nvgpu_cic_log_pending_intrs(g);
#endif
}
@@ -568,14 +568,14 @@ static int nvgpu_init_interrupt_setup(struct gk20a *g)
/**
* Disable all interrupts at the start.
*/
nvgpu_mc_intr_mask(g);
nvgpu_cic_intr_mask(g);
#ifdef CONFIG_NVGPU_NON_FUSA
/**
* For certain chips like gm20b, there is global interrupt control in
* registers mc_intr_en_*_r. Program them here upfront.
*/
nvgpu_mc_intr_enable(g);
nvgpu_cic_intr_enable(g);
#endif
return 0;

7
drivers/gpu/nvgpu/common/ltc/ltc.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,7 @@
#include <nvgpu/dma.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/cic.h>
#include <nvgpu/string.h>
void nvgpu_ltc_remove_support(struct gk20a *g)
@@ -73,8 +74,8 @@ int nvgpu_init_ltc_support(struct gk20a *g)
}
if (g->ops.ltc.intr.configure != NULL) {
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_LTC,
MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_LTC,
NVGPU_CIC_INTR_ENABLE);
g->ops.ltc.intr.configure(g);
}

5
drivers/gpu/nvgpu/common/nvlink/nvlink.c
View File

@@ -27,6 +27,7 @@
#include <nvgpu/device.h>
#include <nvgpu/nvlink_bios.h>
#include <nvgpu/device.h>
#include <nvgpu/cic.h>
#include <nvgpu/errata.h>
#ifdef CONFIG_NVGPU_NVLINK
@@ -235,8 +236,8 @@ int nvgpu_nvlink_early_init(struct gk20a *g)
nvgpu_err(g, "Failed to reset NVLINK unit");
}
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_NVLINK,
MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_NVLINK,
NVGPU_CIC_INTR_ENABLE);
err = g->ops.nvlink.discover_link(g);
if ((err != 0) || (g->nvlink.discovered_links == 0U)) {

5
drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -28,6 +28,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/nvgpu_sgt.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/mc.h>
#include "bus_gk20a.h"
@@ -38,7 +39,7 @@ int gk20a_bus_init_hw(struct gk20a *g)
{
u32 intr_en_mask = 0U;
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_BUS, MC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
/*
* Note: bus_intr_en_0 is for routing intr to stall tree (mc_intr_0)

5
drivers/gpu/nvgpu/hal/bus/bus_tu104.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,7 @@
#include <nvgpu/soc.h>
#include <nvgpu/io.h>
#include <nvgpu/mm.h>
#include <nvgpu/cic.h>
#include <nvgpu/gk20a.h>
#include "bus_tu104.h"
@@ -35,7 +36,7 @@ int tu104_bus_init_hw(struct gk20a *g)
{
u32 intr_en_mask = 0U;
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_BUS, MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE);
/*
* Note: bus_intr_en_0 is for routing intr to stall tree (mc_intr_0)

7
drivers/gpu/nvgpu/hal/ce/ce2_gk20a.c
View File

@@ -1,7 +1,7 @@
/*
* GK20A Graphics Copy Engine (gr host)
*
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -29,6 +29,7 @@
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/cic.h>
#include <nvgpu/mc.h>
#include <nvgpu/channel.h>
#include <nvgpu/engines.h>
@@ -69,8 +70,8 @@ u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
nvgpu_log(g, gpu_dbg_intr, "ce2 non-blocking pipe interrupt");
nvgpu_writel(g, ce2_intr_status_r(),
ce2_intr_status_nonblockpipe_pending_f());
ops |= (NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_NONSTALL_OPS_POST_EVENTS);
ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
}
return ops;
}

5
drivers/gpu/nvgpu/hal/ce/ce_gp10b_fusa.c
View File

@@ -25,6 +25,7 @@
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/nvgpu_err.h>
#include "ce_gp10b.h"
@@ -68,8 +69,8 @@ u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
if ((ce_intr & ce_intr_status_nonblockpipe_pending_f()) != 0U) {
nvgpu_writel(g, ce_intr_status_r(inst_id),
ce_intr_status_nonblockpipe_pending_f());
nonstall_ops |= (NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_NONSTALL_OPS_POST_EVENTS);
nonstall_ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
}
return nonstall_ops;

7
drivers/gpu/nvgpu/hal/fb/intr/fb_intr_gv11b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* GV11B FB
*
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
#include <nvgpu/log.h>
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/cic.h>
#include <nvgpu/mc.h>
#include "hal/fb/fb_gv11b.h"
@@ -47,7 +48,7 @@ void gv11b_fb_intr_enable(struct gk20a *g)
#endif
fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m();
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_HUB, MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_HUB, NVGPU_CIC_INTR_ENABLE);
nvgpu_writel(g, fb_niso_intr_en_set_r(0), mask);
}
@@ -67,7 +68,7 @@ void gv11b_fb_intr_disable(struct gk20a *g)
nvgpu_writel(g, fb_niso_intr_en_clr_r(0), mask);
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_HUB, MC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_HUB, NVGPU_CIC_INTR_DISABLE);
}
void gv11b_fb_intr_isr(struct gk20a *g, u32 intr_unit_bitmask)

5
drivers/gpu/nvgpu/hal/fbpa/fbpa_tu104.c
View File

@@ -1,7 +1,7 @@
/*
* TU104 FBPA
*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -28,6 +28,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/hw/tu104/hw_fbpa_tu104.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/nvgpu_init.h>
#include "hal/fbpa/fbpa_tu104.h"
@@ -40,7 +41,7 @@ int tu104_fbpa_init(struct gk20a *g)
val |= fbpa_ecc_intr_ctrl_sec_intr_en_enabled_f() |
fbpa_ecc_intr_ctrl_ded_intr_en_enabled_f();
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_FBPA, MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FBPA, NVGPU_CIC_INTR_ENABLE);
nvgpu_writel(g, fbpa_ecc_intr_ctrl_r(), val);
/* read back broadcast register */

9
drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c
View File

@@ -1,7 +1,7 @@
/*
* GK20A Graphics FIFO (gr host)
*
* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,7 @@
#include <nvgpu/fifo.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/cic.h>
#include <nvgpu/mc.h>
#include "hal/fifo/fifo_gk20a.h"
@@ -35,9 +36,9 @@
static void enable_fifo_interrupts(struct gk20a *g)
{
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_FIFO, MC_INTR_ENABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_FIFO,
MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO, NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_ENABLE);
g->ops.fifo.intr_0_enable(g, true);
g->ops.fifo.intr_1_enable(g, true);

11
drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* GV11B fifo
*
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -29,6 +29,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/cic.h>
#include <nvgpu/mc.h>
#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
@@ -37,10 +38,10 @@
static void enable_fifo_interrupts(struct gk20a *g)
{
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_FIFO,
MC_INTR_ENABLE);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_FIFO,
MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_ENABLE);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
NVGPU_CIC_INTR_ENABLE);
g->ops.fifo.intr_0_enable(g, true);
g->ops.fifo.intr_1_enable(g, true);

3
drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c
View File

@@ -30,6 +30,7 @@
#include <nvgpu/tsg.h>
#include <nvgpu/rc.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/engines.h>
#include <hal/fifo/fifo_intr_gk20a.h>
@@ -58,7 +59,7 @@ u32 gk20a_fifo_intr_1_isr(struct gk20a *g)
if ((fifo_intr & fifo_intr_0_channel_intr_pending_f()) != 0U) {
nvgpu_writel(g, fifo_intr_0_r(),
fifo_intr_0_channel_intr_pending_f());
return NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE;
return NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE;
}
return 0U;

7
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b_fusa.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,6 +22,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/io.h>
#include <nvgpu/class.h>
#include <nvgpu/static_analysis.h>
@@ -381,8 +382,8 @@ u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g)
/* Clear the interrupt */
nvgpu_writel(g, gr_intr_nonstall_r(),
gr_intr_nonstall_trap_pending_f());
ops |= (NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_NONSTALL_OPS_POST_EVENTS);
ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
}
return ops;
}

21
drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
View File

@@ -1,7 +1,7 @@
/*
* GM20B Master Control
*
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -26,6 +26,7 @@
#include <nvgpu/atomic.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/ltc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
@@ -107,25 +108,25 @@ static u32 gm20b_mc_intr_pending_f(struct gk20a *g, u32 unit)
u32 intr_pending_f = 0;
switch (unit) {
case MC_INTR_UNIT_BUS:
case NVGPU_CIC_INTR_UNIT_BUS:
intr_pending_f = mc_intr_pbus_pending_f();
break;
case MC_INTR_UNIT_PRIV_RING:
case NVGPU_CIC_INTR_UNIT_PRIV_RING:
intr_pending_f = mc_intr_priv_ring_pending_f();
break;
case MC_INTR_UNIT_FIFO:
case NVGPU_CIC_INTR_UNIT_FIFO:
intr_pending_f = mc_intr_pfifo_pending_f();
break;
case MC_INTR_UNIT_LTC:
case NVGPU_CIC_INTR_UNIT_LTC:
intr_pending_f = mc_intr_ltc_pending_f();
break;
case MC_INTR_UNIT_GR:
case NVGPU_CIC_INTR_UNIT_GR:
intr_pending_f = nvgpu_gr_engine_interrupt_mask(g);
break;
case MC_INTR_UNIT_PMU:
case NVGPU_CIC_INTR_UNIT_PMU:
intr_pending_f = mc_intr_mask_0_pmu_enabled_f();
break;
case MC_INTR_UNIT_CE:
case NVGPU_CIC_INTR_UNIT_CE:
intr_pending_f = nvgpu_ce_engine_interrupt_mask(g);
break;
default:
@@ -204,12 +205,12 @@ void gm20b_mc_intr_nonstall_resume(struct gk20a *g)
u32 gm20b_mc_intr_stall(struct gk20a *g)
{
return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
return nvgpu_readl(g, mc_intr_r(NVGPU_CIC_INTR_STALLING));
}
u32 gm20b_mc_intr_nonstall(struct gk20a *g)
{
return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
return nvgpu_readl(g, mc_intr_r(NVGPU_CIC_INTR_NONSTALLING));
}
bool gm20b_mc_is_intr1_pending(struct gk20a *g, u32 unit, u32 mc_intr_1)

61
drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* GP10B master
*
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/engines.h>
#include <nvgpu/device.h>
#include <nvgpu/power_features/pg.h>
@@ -35,13 +36,13 @@
void mc_gp10b_intr_mask(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_CIC_INTR_STALLING),
U32_MAX);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = 0;
g->mc.intr_mask_restore[NVGPU_CIC_INTR_STALLING] = 0;
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_CIC_INTR_NONSTALLING),
U32_MAX);
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = 0;
g->mc.intr_mask_restore[NVGPU_CIC_INTR_NONSTALLING] = 0;
}
static u32 mc_gp10b_intr_pending_f(struct gk20a *g, u32 unit)
@@ -49,28 +50,28 @@ static u32 mc_gp10b_intr_pending_f(struct gk20a *g, u32 unit)
u32 intr_pending_f = 0;
switch (unit) {
case MC_INTR_UNIT_BUS:
case NVGPU_CIC_INTR_UNIT_BUS:
intr_pending_f = mc_intr_pbus_pending_f();
break;
case MC_INTR_UNIT_PRIV_RING:
case NVGPU_CIC_INTR_UNIT_PRIV_RING:
intr_pending_f = mc_intr_priv_ring_pending_f();
break;
case MC_INTR_UNIT_FIFO:
case NVGPU_CIC_INTR_UNIT_FIFO:
intr_pending_f = mc_intr_pfifo_pending_f();
break;
case MC_INTR_UNIT_LTC:
case NVGPU_CIC_INTR_UNIT_LTC:
intr_pending_f = mc_intr_ltc_pending_f();
break;
case MC_INTR_UNIT_GR:
case NVGPU_CIC_INTR_UNIT_GR:
intr_pending_f = nvgpu_gr_engine_interrupt_mask(g);
break;
case MC_INTR_UNIT_PMU:
case NVGPU_CIC_INTR_UNIT_PMU:
intr_pending_f = mc_intr_pmu_pending_f();
break;
case MC_INTR_UNIT_HUB:
case NVGPU_CIC_INTR_UNIT_HUB:
intr_pending_f = mc_intr_replayable_fault_pending_f();
break;
case MC_INTR_UNIT_CE:
case NVGPU_CIC_INTR_UNIT_CE:
intr_pending_f = nvgpu_ce_engine_interrupt_mask(g);
break;
default:
@@ -146,13 +147,13 @@ void mc_gp10b_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
u32 reg = 0U;
if (enable) {
reg = mc_intr_en_set_r(NVGPU_MC_INTR_STALLING);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] |=
reg = mc_intr_en_set_r(NVGPU_CIC_INTR_STALLING);
g->mc.intr_mask_restore[NVGPU_CIC_INTR_STALLING] |=
unit_pending_f;
nvgpu_writel(g, reg, unit_pending_f);
} else {
reg = mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] &=
reg = mc_intr_en_clear_r(NVGPU_CIC_INTR_STALLING);
g->mc.intr_mask_restore[NVGPU_CIC_INTR_STALLING] &=
~unit_pending_f;
nvgpu_writel(g, reg, unit_pending_f);
}
@@ -164,13 +165,13 @@ void mc_gp10b_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
u32 reg = 0U;
if (enable) {
reg = mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING);
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] |=
reg = mc_intr_en_set_r(NVGPU_CIC_INTR_NONSTALLING);
g->mc.intr_mask_restore[NVGPU_CIC_INTR_NONSTALLING] |=
unit_pending_f;
nvgpu_writel(g, reg, unit_pending_f);
} else {
reg = mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING);
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] &=
reg = mc_intr_en_clear_r(NVGPU_CIC_INTR_NONSTALLING);
g->mc.intr_mask_restore[NVGPU_CIC_INTR_NONSTALLING] &=
~unit_pending_f;
nvgpu_writel(g, reg, unit_pending_f);
}
@@ -182,7 +183,7 @@ void mc_gp10b_isr_stall(struct gk20a *g)
u32 i;
const struct nvgpu_device *dev;
mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_CIC_INTR_STALLING));
nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0);
@@ -207,35 +208,35 @@ void mc_gp10b_isr_stall(struct gk20a *g)
u32 mc_gp10b_intr_stall(struct gk20a *g)
{
return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
return nvgpu_readl(g, mc_intr_r(NVGPU_CIC_INTR_STALLING));
}
void mc_gp10b_intr_stall_pause(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), U32_MAX);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_CIC_INTR_STALLING), U32_MAX);
}
void mc_gp10b_intr_stall_resume(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_CIC_INTR_STALLING),
g->mc.intr_mask_restore[NVGPU_CIC_INTR_STALLING]);
}
u32 mc_gp10b_intr_nonstall(struct gk20a *g)
{
return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
return nvgpu_readl(g, mc_intr_r(NVGPU_CIC_INTR_NONSTALLING));
}
void mc_gp10b_intr_nonstall_pause(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_CIC_INTR_NONSTALLING),
U32_MAX);
}
void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
{
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
nvgpu_writel(g, mc_intr_en_set_r(NVGPU_CIC_INTR_NONSTALLING),
g->mc.intr_mask_restore[NVGPU_CIC_INTR_NONSTALLING]);
}
bool mc_gp10b_is_intr1_pending(struct gk20a *g, u32 unit, u32 mc_intr_1)

5
drivers/gpu/nvgpu/hal/mc/mc_gv100.c
View File

@@ -1,7 +1,7 @@
/*
* GV100 master
*
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
#include <nvgpu/types.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include <nvgpu/engines.h>
@@ -42,7 +43,7 @@ bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
u32 *eng_intr_pending)
{
u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_CIC_INTR_STALLING));
u32 stall_intr, eng_intr_mask;
eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, engine_id);

5
drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c
View File

@@ -1,7 +1,7 @@
/*
* GV11B master
*
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
#include <nvgpu/types.h>
#include <nvgpu/io.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>
@@ -40,7 +41,7 @@ bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
u32 *eng_intr_pending)
{
u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_CIC_INTR_STALLING));
u32 stall_intr, eng_intr_mask;
eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, engine_id);

45
drivers/gpu/nvgpu/hal/mc/mc_tu104.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,7 @@
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/ltc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/engines.h>
@@ -142,7 +143,7 @@ static void intr_tu104_nonstall_enable(struct gk20a *g)
u32 intr_mask;
/* Keep NV_PMC_INTR(1) disabled */
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), U32_MAX);
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_CIC_INTR_NONSTALLING), U32_MAX);
/*
* Enable nonstall interrupts in TOP
@@ -187,31 +188,31 @@ static u32 intr_tu104_intr_pending_f(struct gk20a *g, u32 unit)
u32 intr_pending_f = 0;
switch (unit) {
case MC_INTR_UNIT_BUS:
case NVGPU_CIC_INTR_UNIT_BUS:
intr_pending_f = mc_intr_pbus_pending_f();
break;
case MC_INTR_UNIT_PRIV_RING:
case NVGPU_CIC_INTR_UNIT_PRIV_RING:
intr_pending_f = mc_intr_priv_ring_pending_f();
break;
case MC_INTR_UNIT_FIFO:
case NVGPU_CIC_INTR_UNIT_FIFO:
intr_pending_f = mc_intr_pfifo_pending_f();
break;
case MC_INTR_UNIT_LTC:
case NVGPU_CIC_INTR_UNIT_LTC:
intr_pending_f = mc_intr_ltc_pending_f();
break;
case MC_INTR_UNIT_GR:
case NVGPU_CIC_INTR_UNIT_GR:
intr_pending_f = nvgpu_gr_engine_interrupt_mask(g);
break;
case MC_INTR_UNIT_PMU:
case NVGPU_CIC_INTR_UNIT_PMU:
intr_pending_f = mc_intr_pmu_pending_f();
break;
case MC_INTR_UNIT_CE:
case NVGPU_CIC_INTR_UNIT_CE:
intr_pending_f = nvgpu_ce_engine_interrupt_mask(g);
break;
case MC_INTR_UNIT_NVLINK:
case NVGPU_CIC_INTR_UNIT_NVLINK:
intr_pending_f = mc_intr_nvlink_pending_f();
break;
case MC_INTR_UNIT_FBPA:
case NVGPU_CIC_INTR_UNIT_FBPA:
intr_pending_f = mc_intr_pfb_pending_f();
break;
default:
@@ -228,13 +229,13 @@ void intr_tu104_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
u32 reg = 0U;
if (enable) {
reg = mc_intr_en_set_r(NVGPU_MC_INTR_STALLING);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] |=
reg = mc_intr_en_set_r(NVGPU_CIC_INTR_STALLING);
g->mc.intr_mask_restore[NVGPU_CIC_INTR_STALLING] |=
unit_pending_f;
nvgpu_writel(g, reg, unit_pending_f);
} else {
reg = mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] &=
reg = mc_intr_en_clear_r(NVGPU_CIC_INTR_STALLING);
g->mc.intr_mask_restore[NVGPU_CIC_INTR_STALLING] &=
~unit_pending_f;
nvgpu_writel(g, reg, unit_pending_f);
}
@@ -249,11 +250,11 @@ void intr_tu104_mask(struct gk20a *g)
{
u32 size, reg, i;
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), U32_MAX);
g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = 0;
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_CIC_INTR_STALLING), U32_MAX);
g->mc.intr_mask_restore[NVGPU_CIC_INTR_STALLING] = 0;
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), U32_MAX);
g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = 0;
nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_CIC_INTR_NONSTALLING), U32_MAX);
g->mc.intr_mask_restore[NVGPU_CIC_INTR_NONSTALLING] = 0;
size = func_priv_cpu_intr_top_en_clear__size_1_v();
for (i = 0U; i < size; i++) {
@@ -353,8 +354,8 @@ u32 intr_tu104_isr_nonstall(struct gk20a *g)
NV_CPU_INTR_TOP_NONSTALL_SUBTREE)),
nonstall_intr_mask_hi);
ops |= (NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_NONSTALL_OPS_POST_EVENTS);
ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
}
}
@@ -486,7 +487,7 @@ void mc_tu104_isr_stall(struct gk20a *g)
u32 i;
const struct nvgpu_device *dev;
mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
mc_intr_0 = nvgpu_readl(g, mc_intr_r(NVGPU_CIC_INTR_STALLING));
nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0);

9
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -29,6 +29,7 @@
#include <nvgpu/pmu/fw.h>
#include <nvgpu/pmu/debug.h>
#include <nvgpu/pmu/pmu_pg.h>
#include <nvgpu/cic.h>
#include <nvgpu/mc.h>
#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
@@ -448,7 +449,7 @@ void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
nvgpu_log_fn(g, " ");
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_PMU, MC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU, NVGPU_CIC_INTR_DISABLE);
nvgpu_falcon_set_irq(pmu->flcn, false, 0x0, 0x0);
@@ -464,8 +465,8 @@ void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
pwr_falcon_irqmset_swgen0_f(1) |
pwr_falcon_irqmset_swgen1_f(1);
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_PMU,
MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU,
NVGPU_CIC_INTR_ENABLE);
nvgpu_falcon_set_irq(pmu->flcn, true, intr_mask, intr_dest);
}

9
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,7 @@
#include <nvgpu/mm.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/cic.h>
#include <nvgpu/firmware.h>
#include <nvgpu/bug.h>
#ifdef CONFIG_NVGPU_LS_PMU
@@ -446,7 +447,7 @@ void gv11b_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
nvgpu_log_fn(g, " ");
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_PMU, MC_INTR_DISABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU, NVGPU_CIC_INTR_DISABLE);
nvgpu_falcon_set_irq(pmu->flcn, false, intr_mask, intr_dest);
@@ -466,8 +467,8 @@ void gv11b_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable)
#else
intr_mask = pwr_falcon_irqmset_ext_ecc_parity_f(1);
#endif
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_PMU,
MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PMU,
NVGPU_CIC_INTR_ENABLE);
nvgpu_falcon_set_irq(pmu->flcn, true, intr_mask, intr_dest);
}

9
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b_fusa.c
View File

@@ -29,6 +29,7 @@
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/cic.h>
#include <nvgpu/mc.h>
#include "priv_ring_gm20b.h"
@@ -48,8 +49,8 @@ int gm20b_priv_ring_enable(struct gk20a *g)
#ifdef CONFIG_NVGPU_SIM
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
nvgpu_log_info(g, "priv ring is already enabled");
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_PRIV_RING,
MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING,
NVGPU_CIC_INTR_ENABLE);
return 0;
}
#endif
@@ -61,8 +62,8 @@ int gm20b_priv_ring_enable(struct gk20a *g)
/*
* Enable interrupt early on.
*/
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_PRIV_RING,
MC_INTR_ENABLE);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING,
NVGPU_CIC_INTR_ENABLE);
nvgpu_writel(g, pri_ringmaster_command_r(),
pri_ringmaster_command_cmd_enumerate_and_start_ring_f());

428
drivers/gpu/nvgpu/include/nvgpu/cic.h
View File

@@ -25,6 +25,10 @@
#include <nvgpu/log.h>
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include "include/nvgpu/nvgpu_next_cic.h"
#endif
struct nvgpu_err_desc;
/**
* @file
@@ -33,6 +37,145 @@ struct nvgpu_err_desc;
* (CIC) unit.
*/
/**
* @defgroup NVGPU_CIC_INTR_PENDING_DEFINES
*
* Defines of all CIC unit interrupt pending scenarios.
*/
/**
* @ingroup NVGPU_CIC_INTR_PENDING_DEFINES
* Indicates that pending interrupts should be handled in the ISR thread.
*/
#define NVGPU_CIC_INTR_HANDLE 0U
/**
* @ingroup NVGPU_CIC_INTR_PENDING_DEFINES
* Indicates that pending interrupts are erroneous and should be cleared.
*/
#define NVGPU_CIC_INTR_UNMASK BIT32(0)
/**
* @ingroup NVGPU_CIC_INTR_PENDING_DEFINES
* Indicates that there are no pending interrupts.
*/
#define NVGPU_CIC_INTR_NONE BIT32(1)
/**
* @ingroup NVGPU_CIC_INTR_PENDING_DEFINES
* Indicates that quiesce state is pending. This basically means there is no
* need to handle interrupts (if any) as driver will enter quiesce state.
*/
#define NVGPU_CIC_INTR_QUIESCE_PENDING BIT32(2)
/**
* @defgroup NVGPU_CIC_INTR_TYPE_DEFINES
*
* Defines of all CIC unit interrupt types.
*/
/**
* @ingroup NVGPU_CIC_INTR_TYPE_DEFINES
* Index for accessing registers corresponding to stalling interrupts.
*/
#define NVGPU_CIC_INTR_STALLING 0U
/**
* @ingroup NVGPU_CIC_INTR_TYPE_DEFINES
* Index for accessing registers corresponding to non-stalling
* interrupts.
*/
#define NVGPU_CIC_INTR_NONSTALLING 1U
/**
* @defgroup NVGPU_CIC_NONSTALL_OP_DEFINES
*
* Defines of all operations that are required to be executed on non stall
* workqueue.
*/
/**
* @ingroup NVGPU_CIC_NONSTALL_OP_DEFINES
* Wakeup semaphore operation.
*/
#define NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE BIT32(0)
/**
* @ingroup NVGPU_CIC_NONSTALL_OP_DEFINES
* Post events operation.
*/
#define NVGPU_CIC_NONSTALL_OPS_POST_EVENTS BIT32(1)
/**
* @defgroup NVGPU_CIC_INTR_UNIT_DEFINES
*
* Defines of all units intended to be used by any interrupt related
* HAL that requires unit as parameter.
*/
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for Bus unit.
*/
#define NVGPU_CIC_INTR_UNIT_BUS 0
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for PRIV_RING unit.
*/
#define NVGPU_CIC_INTR_UNIT_PRIV_RING 1
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for FIFO unit.
*/
#define NVGPU_CIC_INTR_UNIT_FIFO 2
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for LTC unit.
*/
#define NVGPU_CIC_INTR_UNIT_LTC 3
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for HUB unit.
*/
#define NVGPU_CIC_INTR_UNIT_HUB 4
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for GR unit.
*/
#define NVGPU_CIC_INTR_UNIT_GR 5
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for PMU unit.
*/
#define NVGPU_CIC_INTR_UNIT_PMU 6
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for CE unit.
*/
#define NVGPU_CIC_INTR_UNIT_CE 7
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for NVLINK unit.
*/
#define NVGPU_CIC_INTR_UNIT_NVLINK 8
/**
* @ingroup NVGPU_CIC_INTR_UNIT_DEFINES
* CIC interrupt for FBPA unit.
*/
#define NVGPU_CIC_INTR_UNIT_FBPA 9
/**
* @defgroup NVGPU_CIC_INTR_ENABLE_DEFINES
*
* Defines for CIC unit interrupt enabling/disabling.
*/
/**
* @ingroup NVGPU_CIC_INTR_ENABLE_DEFINES
* Value to be passed to mc.intr_*_unit_config to enable the interrupt.
*/
#define NVGPU_CIC_INTR_ENABLE true
/**
* @ingroup NVGPU_CIC_INTR_ENABLE_DEFINES
* Value to be passed to mc.intr_*_unit_config to disable the interrupt.
*/
#define NVGPU_CIC_INTR_DISABLE false
/*
* Requires a string literal for the format - notice the string
* concatination.
@@ -203,4 +346,289 @@ int nvgpu_cic_report_err_safety_services(struct gk20a *g,
* @retval -EINVAL if CIC is not initialized.
*/
int nvgpu_cic_get_num_hw_modules(struct gk20a *g);
/**
* @brief Top half of stall interrupt ISR.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked by stall interrupt ISR to check if there are
* any pending stall interrupts. The function will return the action to
* be taken based on stall interrupt, gpu and quiesce status.
*
* @retval NVGPU_CIC_INTR_HANDLE if stall interrupts are pending.
* @retval NVGPU_CIC_INTR_UNMASK if GPU is powered off.
* @retval NVGPU_CIC_INTR_NONE if none of the stall interrupts are pending.
* @retval NVGPU_CIC_INTR_QUIESCE_PENDING if quiesce is pending.
*/
u32 nvgpu_cic_intr_stall_isr(struct gk20a *g);
/**
* @brief Bottom half of stall interrupt ISR.
*
* @param g [in] The GPU driver struct.
*
* This function is called to take action based on pending stall interrupts.
* The unit ISR functions are invoked based on triggered stall interrupts.
*/
void nvgpu_cic_intr_stall_handle(struct gk20a *g);
/**
* @brief Top half of nonstall interrupt ISR.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked by nonstall interrupt ISR to check if there are
* any pending nonstall interrupts. The function will return the action to
* be taken based on nonstall interrupt, gpu and quiesce status.
*
* @retval NVGPU_CIC_INTR_HANDLE if nonstall interrupts are pending.
* @retval NVGPU_CIC_INTR_UNMASK if GPU is powered off.
* @retval NVGPU_CIC_INTR_NONE if none of the nonstall interrupts are pending.
* @retval NVGPU_CIC_INTR_QUIESCE_PENDING if quiesce is pending.
*/
u32 nvgpu_cic_intr_nonstall_isr(struct gk20a *g);
/**
* @brief Bottom half of nonstall interrupt ISR.
*
* @param g [in] The GPU driver struct.
*
* This function is called to take action based on pending nonstall interrupts.
* Based on triggered nonstall interrupts, this function will invoke
* nonstall operations.
*/
void nvgpu_cic_intr_nonstall_handle(struct gk20a *g);
/**
* @brief Wait for the stalling interrupts to complete.
*
* @param g [in] The GPU driver struct.
* @param timeout [in] Timeout
*
* Steps:
* - Get the stalling interrupts atomic count.
* - Wait for #timeout duration on the condition variable
* #sw_irq_stall_last_handled_cond until #sw_irq_stall_last_handled
* becomes greater than or equal to previously read stalling
* interrupt atomic count.
*
* @retval 0 if wait completes successfully.
* @retval -ETIMEDOUT if wait completes without stalling interrupts
* completing.
*/
int nvgpu_cic_wait_for_stall_interrupts(struct gk20a *g, u32 timeout);
/**
* @brief Wait for the non-stalling interrupts to complete.
*
* @param g [in] The GPU driver struct.
* @param timeout [in] Timeout
*
* Steps:
* - Get the non-stalling interrupts atomic count.
* - Wait for #timeout duration on the condition variable
* #sw_irq_nonstall_last_handled_cond until #sw_irq_nonstall_last_handled
* becomes greater than or equal to previously read non-stalling
* interrupt atomic count.
*
* @retval 0 if wait completes successfully.
* @retval -ETIMEDOUT if wait completes without nonstalling interrupts
* completing.
*/
int nvgpu_cic_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout);
/**
* @brief Wait for the interrupts to complete.
*
* @param g [in] The GPU driver struct.
*
* While freeing the channel or entering SW quiesce state, nvgpu driver needs
* to wait until all scheduled interrupt handlers have completed. This is
* because the interrupt handlers could access data structures after freeing.
* Steps:
* - Wait for stalling interrupts to complete with timeout disabled.
* - Wait for non-stalling interrupts to complete with timeout disabled.
*/
void nvgpu_cic_wait_for_deferred_interrupts(struct gk20a *g);
/**
* @brief Clear the GPU device interrupts at master level.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked before powering on, powering off or finishing
* SW quiesce of nvgpu driver.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Write U32_MAX to the stalling interrupts enable clear register.
* mc_intr_en_clear_r are write only registers which clear
* the corresponding bit in INTR_EN whenever a 1 is written
* to it.
* - Set g->mc.intr_mask_restore[NVGPU_CIC_INTR_STALLING] and
* g->mc.intr_mask_restore[NVGPU_CIC_INTR_NONSTALLING] to 0.
* - Write U32_MAX to the non-stalling interrupts enable clear register.
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_mask(struct gk20a *g);
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_cic_log_pending_intrs(struct gk20a *g);
void nvgpu_cic_intr_enable(struct gk20a *g);
#endif
/**
* @brief Enable/Disable the stalling interrupts for given GPU unit at the
* master level.
*
* @param g [in] The GPU driver struct.
* @param unit [in] Value designating the GPU HW unit/engine
* controlled by MC. Supported values are:
* - #NVGPU_CIC_INTR_UNIT_BUS
* - #NVGPU_CIC_INTR_UNIT_PRIV_RING
* - #NVGPU_CIC_INTR_UNIT_FIFO
* - #NVGPU_CIC_INTR_UNIT_LTC
* - #NVGPU_CIC_INTR_UNIT_HUB
* - #NVGPU_CIC_INTR_UNIT_GR
* - #NVGPU_CIC_INTR_UNIT_PMU
* - #NVGPU_CIC_INTR_UNIT_CE
* - #NVGPU_CIC_INTR_UNIT_NVLINK
* - #NVGPU_CIC_INTR_UNIT_FBPA
* @param enable [in] Boolean control to enable/disable the stalling
* interrupt. Supported values are:
* - #NVGPU_CIC_INTR_ENABLE
* - #NVGPU_CIC_INTR_DISABLE
*
* During a unit's init routine, this function is invoked to enable the
* unit's stall interrupts.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Get the interrupt bitmask for \a unit.
* - If interrupt is to be enabled
* - Set interrupt bitmask in
* #intr_mask_restore[#NVGPU_CIC_INTR_STALLING].
* - Write the interrupt bitmask to the register
* mc_intr_en_set_r(#NVGPU_CIC_INTR_STALLING).
* - Else
* - Clear interrupt bitmask in
* #intr_mask_restore[#NVGPU_CIC_INTR_STALLING].
* - Write the interrupt bitmask to the register
* mc_intr_en_clear_r(#NVGPU_CIC_INTR_STALLING).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
/**
* @brief Enable/Disable the non-stalling interrupts for given GPU unit at the
* master level.
*
* @param g [in] The GPU driver struct.
* @param unit [in] Value designating the GPU HW unit/engine
* controlled by MC. Supported values are:
* - #NVGPU_CIC_INTR_UNIT_BUS
* - #NVGPU_CIC_INTR_UNIT_PRIV_RING
* - #NVGPU_CIC_INTR_UNIT_FIFO
* - #NVGPU_CIC_INTR_UNIT_LTC
* - #NVGPU_CIC_INTR_UNIT_HUB
* - #NVGPU_CIC_INTR_UNIT_GR
* - #NVGPU_CIC_INTR_UNIT_PMU
* - #NVGPU_CIC_INTR_UNIT_CE
* - #NVGPU_CIC_INTR_UNIT_NVLINK
* - #NVGPU_CIC_INTR_UNIT_FBPA
* @param enable [in] Boolean control to enable/disable the stalling
* interrupt. Supported values are:
* - #NVGPU_CIC_INTR_ENABLE
* - #NVGPU_CIC_INTR_DISABLE
*
* During a unit's init routine, this function is invoked to enable the
* unit's nostall interrupts.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Get the interrupt bitmask for \a unit.
* - If interrupt is to be enabled
* - Set interrupt bitmask in
* #intr_mask_restore[#NVGPU_CIC_INTR_NONSTALLING].
* - Write the interrupt bitmask to the register
* mc_intr_en_set_r(#NVGPU_CIC_INTR_NONSTALLING).
* - Else
* - Clear interrupt bitmask in
* #intr_mask_restore[#NVGPU_CIC_INTR_NONSTALLING].
* - Write the interrupt bitmask to the register
* mc_intr_en_clear_r(#NVGPU_CIC_INTR_NONSTALLING).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable);
/**
* @brief Disable/Pause the stalling interrupts.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked to disable the stalling interrupts before
* the ISR is executed.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Write U32_MAX to the stalling interrupts enable clear register
* (mc_intr_en_clear_r(#NVGPU_CIC_INTR_STALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_stall_pause(struct gk20a *g);
/**
* @brief Enable/Resume the stalling interrupts.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked to enable the stalling interrupts after
* the ISR is executed.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Enable stalling interrupts as configured during #intr_stall_unit_config
* - Write #intr_mask_restore[#NVGPU_CIC_INTR_STALLING] to the stalling
* interrupts enable set register (mc_intr_en_set_r(#NVGPU_CIC_INTR_STALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_stall_resume(struct gk20a *g);
/**
* @brief Disable/Pause the non-stalling interrupts.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked to disable the non-stalling interrupts
* before the ISR is executed.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Write U32_MAX to the non-stalling interrupts enable clear register
* (mc_intr_en_clear_r(#NVGPU_CIC_INTR_NONSTALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_nonstall_pause(struct gk20a *g);
/**
* @brief Enable/Resume the non-stalling interrupts.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked to enable the non-stalling interrupts after
* the ISR is executed.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Enable non-stalling interrupts as configured during
* #intr_nonstall_unit_config.
* - Write #intr_mask_restore[#NVGPU_CIC_INTR_NONSTALLING]
* to the non-stalling interrupts enable set register
* (mc_intr_en_set_r(#NVGPU_CIC_INTR_NONSTALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_cic_intr_nonstall_resume(struct gk20a *g);
#endif /* NVGPU_CIC_H */

4
drivers/gpu/nvgpu/include/nvgpu/gops/ce.h
View File

@@ -73,8 +73,8 @@ struct gops_ce {
* Steps:
* - Read ce_intr_status_r corresponding to \a inst_id.
* - If nonblocking pipe interrupt is pending,
* - Get bitmask of #NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE and
* #NVGPU_NONSTALL_OPS_POST_EVENTS operations.
* - Get bitmask of #NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE and
* #NVGPU_CIC_NONSTALL_OPS_POST_EVENTS operations.
* - Clear the interrupt.
*
* @return Bitmask of operations that will need to be executed on

2
drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h
View File

@@ -149,7 +149,7 @@ struct gops_fifo {
* - Read interrupt status.
* - Clear channel interrupt if pending.
*
* @return: #NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE
* @return: #NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE
*/
u32 (*intr_1_isr)(struct gk20a *g);

28
drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
View File

@@ -79,9 +79,9 @@ struct gops_mc {
*
* Steps:
* - Read and return the value of register
* mc_intr_r(#NVGPU_MC_INTR_STALLING).
* mc_intr_r(#NVGPU_CIC_INTR_STALLING).
*
* @return value read from mc_intr_r(#NVGPU_MC_INTR_STALLING).
* @return value read from mc_intr_r(#NVGPU_CIC_INTR_STALLING).
*/
u32 (*intr_stall)(struct gk20a *g);
@@ -95,7 +95,7 @@ struct gops_mc {
* stalling interrupt for servicing it.
*
* Steps:
* - Read mc_intr_r(#NVGPU_MC_INTR_STALLING) register to get the
* - Read mc_intr_r(#NVGPU_CIC_INTR_STALLING) register to get the
* stalling interrupts reported.
* - For the FIFO engines with pending interrupt invoke corresponding
* handlers.
@@ -106,19 +106,19 @@ struct gops_mc {
* - Invoke g->ops.fb.intr.isr if HUB interrupt is pending, determined
* by calling g->ops.mc.is_intr_hub_pending.
* - Invoke g->ops.fifo.intr_0_isr if FIFO interrupt is pending. The
* FIFO interrupt bit in mc_intr_r(#NVGPU_MC_INTR_STALLING) is
* FIFO interrupt bit in mc_intr_r(#NVGPU_CIC_INTR_STALLING) is
* mc_intr_pfifo_pending_f.
* - Invoke g->ops.pmu.pmu_isr if PMU interrupt is pending.
* The PMU interrupt bit in mc_intr_r(#NVGPU_MC_INTR_STALLING)
* The PMU interrupt bit in mc_intr_r(#NVGPU_CIC_INTR_STALLING)
* is mc_intr_pmu_pending_f.
* - Invoke g->ops.priv_ring.isr if PRIV_RING interrupt is pending.
* The PRIV_RING interrupt bit in mc_intr_r(#NVGPU_MC_INTR_STALLING)
* The PRIV_RING interrupt bit in mc_intr_r(#NVGPU_CIC_INTR_STALLING)
* is mc_intr_priv_ring_pending_f.
* - Invoke g->ops.mc.ltc_isr if LTC interrupt is pending. The
* LTC interrupt bit in mc_intr_r(#NVGPU_MC_INTR_STALLING) is
* LTC interrupt bit in mc_intr_r(#NVGPU_CIC_INTR_STALLING) is
* mc_intr_ltc_pending_f.
* - Invoke g->ops.bus.isr if BUS interrupt is pending. The
* BUS interrupt bit in mc_intr_r(#NVGPU_MC_INTR_STALLING) is
* BUS interrupt bit in mc_intr_r(#NVGPU_CIC_INTR_STALLING) is
* mc_intr_pbus_pending_f.
*/
void (*isr_stall)(struct gk20a *g);
@@ -133,9 +133,9 @@ struct gops_mc {
*
* Steps:
* - Read and return the value of the register
* mc_intr_r(#NVGPU_MC_INTR_NONSTALLING).
* mc_intr_r(#NVGPU_CIC_INTR_NONSTALLING).
*
* @return value read from mc_intr_r(#NVGPU_MC_INTR_NONSTALLING).
* @return value read from mc_intr_r(#NVGPU_CIC_INTR_NONSTALLING).
*/
u32 (*intr_nonstall)(struct gk20a *g);
@@ -149,7 +149,7 @@ struct gops_mc {
* non-stalling interrupt for servicing it.
*
* Steps:
* - Read mc_intr_r(#NVGPU_MC_INTR_NONSTALLING) register to get the
* - Read mc_intr_r(#NVGPU_CIC_INTR_NONSTALLING) register to get the
* non-stalling interrupts reported.
* - Invoke g->ops.fifo.intr_1_isr if FIFO non-stalling interrupt
* is pending, determined by calling mc_intr_pfifo_pending_f.
@@ -176,17 +176,17 @@ struct gops_mc {
* This function is invoked while polling for preempt completion.
*
* Steps:
* - Read mc_intr_r(#NVGPU_MC_INTR_STALLING) register to get
* - Read mc_intr_r(#NVGPU_CIC_INTR_STALLING) register to get
* the interrupts reported.
* - Get the engine interrupt mask corresponding to \a engine_id.
* - Check if the bits for engine interrupt mask are set in the
* mc_intr_r(#NVGPU_MC_INTR_STALLING) register by AND'ing values
* mc_intr_r(#NVGPU_CIC_INTR_STALLING) register by AND'ing values
* read in above two steps. Store the result in \a eng_intr_pending.
* - Initialize the stalling interrupt mask with bitmask for FIFO, HUB,
* PRIV_RING, PBUS, LTC unit interrupts.
* - Return true if bits from above stalling interrupt mask or the
* engine interrupt mask are set in the
* mc_intr_r(#NVGPU_MC_INTR_STALLING) register. Else, return false.
* mc_intr_r(#NVGPU_CIC_INTR_STALLING) register. Else, return false.
*
* @return true if stalling or engine interrupt is pending, else false.
*/

429
drivers/gpu/nvgpu/include/nvgpu/mc.h
View File

@@ -108,7 +108,7 @@
* + include/nvgpu/gops/mc.h
*
* Following interface is common function.
* + nvgpu_wait_for_deferred_interrupts()
* + nvgpu_cic_wait_for_deferred_interrupts()
*/
@@ -163,145 +163,6 @@ struct nvgpu_device;
/** Bit offset of the Architecture field in the HW version register */
#define NVGPU_GPU_ARCHITECTURE_SHIFT 4U
/**
* @defgroup NVGPU_MC_INTR_PENDING_DEFINES
*
* Defines of all MC unit interrupt pending scenarios.
*/
/**
* @ingroup NVGPU_MC_INTR_PENDING_DEFINES
* Indicates that pending interrupts should be handled in the ISR thread.
*/
#define NVGPU_INTR_HANDLE 0U
/**
* @ingroup NVGPU_MC_INTR_PENDING_DEFINES
* Indicates that pending interrupts are erroneous and should be cleared.
*/
#define NVGPU_INTR_UNMASK BIT32(0)
/**
* @ingroup NVGPU_MC_INTR_PENDING_DEFINES
* Indicates that there are no pending interrupts.
*/
#define NVGPU_INTR_NONE BIT32(1)
/**
* @ingroup NVGPU_MC_INTR_PENDING_DEFINES
* Indicates that quiesce state is pending. This basically means there is no
* need to handle interrupts (if any) as driver will enter quiesce state.
*/
#define NVGPU_INTR_QUIESCE_PENDING BIT32(2)
/**
* @defgroup NVGPU_MC_INTR_TYPE_DEFINES
*
* Defines of all MC unit interrupt types.
*/
/**
* @ingroup NVGPU_MC_INTR_TYPE_DEFINES
* Index for accessing registers corresponding to stalling interrupts.
*/
#define NVGPU_MC_INTR_STALLING 0U
/**
* @ingroup NVGPU_MC_INTR_TYPE_DEFINES
* Index for accessing registers corresponding to non-stalling
* interrupts.
*/
#define NVGPU_MC_INTR_NONSTALLING 1U
/**
* @defgroup NVGPU_NONSTALL_OP_DEFINES
*
* Defines of all operations that are required to be executed on non stall
* workqueue.
*/
/**
* @ingroup NVGPU_NONSTALL_OP_DEFINES
* Wakeup semaphore operation.
*/
#define NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE BIT32(0)
/**
* @ingroup NVGPU_NONSTALL_OP_DEFINES
* Post events operation.
*/
#define NVGPU_NONSTALL_OPS_POST_EVENTS BIT32(1)
/**
* @defgroup NVGPU_MC_INTR_UNIT_DEFINES
*
* Defines of all units intended to be used by any interrupt related
* HAL that requires unit as parameter.
*/
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for Bus unit.
*/
#define MC_INTR_UNIT_BUS 0
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for PRIV_RING unit.
*/
#define MC_INTR_UNIT_PRIV_RING 1
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for FIFO unit.
*/
#define MC_INTR_UNIT_FIFO 2
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for LTC unit.
*/
#define MC_INTR_UNIT_LTC 3
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for HUB unit.
*/
#define MC_INTR_UNIT_HUB 4
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for GR unit.
*/
#define MC_INTR_UNIT_GR 5
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for PMU unit.
*/
#define MC_INTR_UNIT_PMU 6
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for CE unit.
*/
#define MC_INTR_UNIT_CE 7
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for NVLINK unit.
*/
#define MC_INTR_UNIT_NVLINK 8
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for FBPA unit.
*/
#define MC_INTR_UNIT_FBPA 9
/**
* @defgroup NVGPU_MC_INTR_ENABLE_DEFINES
*
* Defines for MC unit interrupt enabling/disabling.
*/
/**
* @ingroup NVGPU_MC_INTR_ENABLE_DEFINES
* Value to be passed to mc.intr_*_unit_config to enable the interrupt.
*/
#define MC_INTR_ENABLE true
/**
* @ingroup NVGPU_MC_INTR_ENABLE_DEFINES
* Value to be passed to mc.intr_*_unit_config to disable the interrupt.
*/
#define MC_INTR_DISABLE false
/**
* This struct holds the variables needed to manage the configuration and
* interrupt handling of the units/engines.
@@ -325,7 +186,7 @@ struct nvgpu_mc {
* One of the condition variables needed to keep track of deferred
* interrupts.
* The condition variable that is signalled upon handling of the
* stalling interrupt. Function #nvgpu_wait_for_stall_interrupts
* stalling interrupt. Function #nvgpu_cic_wait_for_stall_interrupts
* waits on this condition variable.
*/
struct nvgpu_cond sw_irq_stall_last_handled_cond;
@@ -341,7 +202,7 @@ struct nvgpu_mc {
* One of the condition variables needed to keep track of deferred
* interrupts.
* The condition variable that is signalled upon handling of the
* non-stalling interrupt. Function #nvgpu_wait_for_nonstall_interrupts
* non-stalling interrupt. Function #nvgpu_cic_wait_for_nonstall_interrupts
* waits on this condition variable.
*/
struct nvgpu_cond sw_irq_nonstall_last_handled_cond;
@@ -361,237 +222,6 @@ struct nvgpu_mc {
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
};
/**
* @brief Wait for the stalling interrupts to complete.
*
* @param g [in] The GPU driver struct.
* @param timeout [in] Timeout
*
* Steps:
* - Get the stalling interrupts atomic count.
* - Wait for #timeout duration on the condition variable
* #sw_irq_stall_last_handled_cond until #sw_irq_stall_last_handled
* becomes greater than or equal to previously read stalling
* interrupt atomic count.
*
* @retval 0 if wait completes successfully.
* @retval -ETIMEDOUT if wait completes without stalling interrupts
* completing.
*/
int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout);
/**
* @brief Wait for the non-stalling interrupts to complete.
*
* @param g [in] The GPU driver struct.
* @param timeout [in] Timeout
*
* Steps:
* - Get the non-stalling interrupts atomic count.
* - Wait for #timeout duration on the condition variable
* #sw_irq_nonstall_last_handled_cond until #sw_irq_nonstall_last_handled
* becomes greater than or equal to previously read non-stalling
* interrupt atomic count.
*
* @retval 0 if wait completes successfully.
* @retval -ETIMEDOUT if wait completes without nonstalling interrupts
* completing.
*/
int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout);
/**
* @brief Wait for the interrupts to complete.
*
* @param g [in] The GPU driver struct.
*
* While freeing the channel or entering SW quiesce state, nvgpu driver needs
* to wait until all scheduled interrupt handlers have completed. This is
* because the interrupt handlers could access data structures after freeing.
* Steps:
* - Wait for stalling interrupts to complete with timeout disabled.
* - Wait for non-stalling interrupts to complete with timeout disabled.
*/
void nvgpu_wait_for_deferred_interrupts(struct gk20a *g);
/**
* @brief Clear the GPU device interrupts at master level.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked before powering on, powering off or finishing
* SW quiesce of nvgpu driver.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Write U32_MAX to the stalling interrupts enable clear register.
* mc_intr_en_clear_r are write only registers which clear
* the corresponding bit in INTR_EN whenever a 1 is written
* to it.
* - Set g->mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] and
* g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] to 0.
* - Write U32_MAX to the non-stalling interrupts enable clear register.
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_mc_intr_mask(struct gk20a *g);
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_mc_log_pending_intrs(struct gk20a *g);
void nvgpu_mc_intr_enable(struct gk20a *g);
#endif
/**
* @brief Enable/Disable the stalling interrupts for given GPU unit at the
* master level.
*
* @param g [in] The GPU driver struct.
* @param unit [in] Value designating the GPU HW unit/engine
* controlled by MC. Supported values are:
* - #MC_INTR_UNIT_BUS
* - #MC_INTR_UNIT_PRIV_RING
* - #MC_INTR_UNIT_FIFO
* - #MC_INTR_UNIT_LTC
* - #MC_INTR_UNIT_HUB
* - #MC_INTR_UNIT_GR
* - #MC_INTR_UNIT_PMU
* - #MC_INTR_UNIT_CE
* - #MC_INTR_UNIT_NVLINK
* - #MC_INTR_UNIT_FBPA
* @param enable [in] Boolean control to enable/disable the stalling
* interrupt. Supported values are:
* - #MC_INTR_ENABLE
* - #MC_INTR_DISABLE
*
* During a unit's init routine, this function is invoked to enable the
* unit's stall interrupts.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Get the interrupt bitmask for \a unit.
* - If interrupt is to be enabled
* - Set interrupt bitmask in
* #intr_mask_restore[#NVGPU_MC_INTR_STALLING].
* - Write the interrupt bitmask to the register
* mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING).
* - Else
* - Clear interrupt bitmask in
* #intr_mask_restore[#NVGPU_MC_INTR_STALLING].
* - Write the interrupt bitmask to the register
* mc_intr_en_clear_r(#NVGPU_MC_INTR_STALLING).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
/**
* @brief Enable/Disable the non-stalling interrupts for given GPU unit at the
* master level.
*
* @param g [in] The GPU driver struct.
* @param unit [in] Value designating the GPU HW unit/engine
* controlled by MC. Supported values are:
* - #MC_INTR_UNIT_BUS
* - #MC_INTR_UNIT_PRIV_RING
* - #MC_INTR_UNIT_FIFO
* - #MC_INTR_UNIT_LTC
* - #MC_INTR_UNIT_HUB
* - #MC_INTR_UNIT_GR
* - #MC_INTR_UNIT_PMU
* - #MC_INTR_UNIT_CE
* - #MC_INTR_UNIT_NVLINK
* - #MC_INTR_UNIT_FBPA
* @param enable [in] Boolean control to enable/disable the stalling
* interrupt. Supported values are:
* - #MC_INTR_ENABLE
* - #MC_INTR_DISABLE
*
* During a unit's init routine, this function is invoked to enable the
* unit's nostall interrupts.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Get the interrupt bitmask for \a unit.
* - If interrupt is to be enabled
* - Set interrupt bitmask in
* #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING].
* - Write the interrupt bitmask to the register
* mc_intr_en_set_r(#NVGPU_MC_INTR_NONSTALLING).
* - Else
* - Clear interrupt bitmask in
* #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING].
* - Write the interrupt bitmask to the register
* mc_intr_en_clear_r(#NVGPU_MC_INTR_NONSTALLING).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_mc_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable);
/**
* @brief Disable/Pause the stalling interrupts.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked to disable the stalling interrupts before
* the ISR is executed.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Write U32_MAX to the stalling interrupts enable clear register
* (mc_intr_en_clear_r(#NVGPU_MC_INTR_STALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_mc_intr_stall_pause(struct gk20a *g);
/**
* @brief Enable/Resume the stalling interrupts.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked to enable the stalling interrupts after
* the ISR is executed.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Enable stalling interrupts as configured during #intr_stall_unit_config
* - Write #intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the stalling
* interrupts enable set register (mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_mc_intr_stall_resume(struct gk20a *g);
/**
* @brief Disable/Pause the non-stalling interrupts.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked to disable the non-stalling interrupts
* before the ISR is executed.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Write U32_MAX to the non-stalling interrupts enable clear register
* (mc_intr_en_clear_r(#NVGPU_MC_INTR_NONSTALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_mc_intr_nonstall_pause(struct gk20a *g);
/**
* @brief Enable/Resume the non-stalling interrupts.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked to enable the non-stalling interrupts after
* the ISR is executed.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Enable non-stalling interrupts as configured during
* #intr_nonstall_unit_config.
* - Write #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING]
* to the non-stalling interrupts enable set register
* (mc_intr_en_set_r(#NVGPU_MC_INTR_NONSTALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
void nvgpu_mc_intr_nonstall_resume(struct gk20a *g);
/**
* @brief Reset given HW unit(s).
*
@@ -652,57 +282,4 @@ int nvgpu_mc_reset_dev(struct gk20a *g, const struct nvgpu_device *dev);
*/
int nvgpu_mc_reset_devtype(struct gk20a *g, u32 devtype);
/**
* @brief Top half of stall interrupt ISR.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked by stall interrupt ISR to check if there are
* any pending stall interrupts. The function will return the action to
* be taken based on stall interrupt, gpu and quiesce status.
*
* @retval NVGPU_INTR_HANDLE if stall interrupts are pending.
* @retval NVGPU_INTR_UNMASK if GPU is powered off.
* @retval NVGPU_INTR_NONE if none of the stall interrupts are pending.
* @retval NVGPU_INTR_QUIESCE_PENDING if quiesce is pending.
*/
u32 nvgpu_intr_stall_isr(struct gk20a *g);
/**
* @brief Bottom half of stall interrupt ISR.
*
* @param g [in] The GPU driver struct.
*
* This function is called to take action based on pending stall interrupts.
* The unit ISR functions are invoked based on triggered stall interrupts.
*/
void nvgpu_intr_stall_handle(struct gk20a *g);
/**
* @brief Top half of nonstall interrupt ISR.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked by nonstall interrupt ISR to check if there are
* any pending nonstall interrupts. The function will return the action to
* be taken based on nonstall interrupt, gpu and quiesce status.
*
* @retval NVGPU_INTR_HANDLE if nonstall interrupts are pending.
* @retval NVGPU_INTR_UNMASK if GPU is powered off.
* @retval NVGPU_INTR_NONE if none of the nonstall interrupts are pending.
* @retval NVGPU_INTR_QUIESCE_PENDING if quiesce is pending.
*/
u32 nvgpu_intr_nonstall_isr(struct gk20a *g);
/**
* @brief Bottom half of nonstall interrupt ISR.
*
* @param g [in] The GPU driver struct.
*
* This function is called to take action based on pending nonstall interrupts.
* Based on triggered nonstall interrupts, this function will invoke
* nonstall operations.
*/
void nvgpu_intr_nonstall_handle(struct gk20a *g);
#endif

17
drivers/gpu/nvgpu/os/linux/module.c
View File

@@ -61,6 +61,7 @@
#include <nvgpu/cyclestats_snapshot.h>
#include <nvgpu/nvgpu_init.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include "platform_gk20a.h"
#include "sysfs.h"
@@ -928,32 +929,32 @@ u64 nvgpu_resource_addr(struct platform_device *dev, int i)
static irqreturn_t gk20a_intr_isr_stall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
u32 err = nvgpu_intr_stall_isr(g);
u32 err = nvgpu_cic_intr_stall_isr(g);
return err == NVGPU_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
return err == NVGPU_CIC_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
}
static irqreturn_t gk20a_intr_thread_isr_stall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
nvgpu_intr_stall_handle(g);
nvgpu_cic_intr_stall_handle(g);
return IRQ_HANDLED;
}
static irqreturn_t gk20a_intr_isr_nonstall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
u32 err = nvgpu_intr_nonstall_isr(g);
u32 err = nvgpu_cic_intr_nonstall_isr(g);
return err == NVGPU_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
return err == NVGPU_CIC_INTR_HANDLE ? IRQ_WAKE_THREAD : IRQ_NONE;
}
static irqreturn_t gk20a_intr_thread_isr_nonstall(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
nvgpu_intr_nonstall_handle(g);
nvgpu_cic_intr_nonstall_handle(g);
return IRQ_HANDLED;
}
@@ -1498,7 +1499,7 @@ int nvgpu_wait_for_gpu_idle(struct gk20a *g)
goto out;
}
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
out:
return ret;
}
@@ -1517,7 +1518,7 @@ void gk20a_driver_start_unload(struct gk20a *g)
nvgpu_wait_for_idle(g);
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
}
static inline void set_gk20a(struct platform_device *pdev, struct gk20a *gk20a)

13
drivers/gpu/nvgpu/os/linux/pci.c
View File

@@ -24,6 +24,7 @@
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/kmem.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/enabled.h>
#include <nvgpu/errata.h>
#include <nvgpu/nvlink_probe.h>
@@ -325,8 +326,8 @@ static struct pci_device_id nvgpu_pci_table[] = {
static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
u32 ret_stall = nvgpu_intr_stall_isr(g);
u32 ret_nonstall = nvgpu_intr_nonstall_isr(g);
u32 ret_stall = nvgpu_cic_intr_stall_isr(g);
u32 ret_nonstall = nvgpu_cic_intr_nonstall_isr(g);
#if defined(CONFIG_PCI_MSI)
/* Send MSI EOI */
@@ -334,8 +335,8 @@ static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id)
g->ops.xve.rearm_msi(g);
#endif
if ((ret_stall == NVGPU_INTR_HANDLE) ||
(ret_nonstall == NVGPU_INTR_HANDLE)) {
if ((ret_stall == NVGPU_CIC_INTR_HANDLE) ||
(ret_nonstall == NVGPU_CIC_INTR_HANDLE)) {
return IRQ_WAKE_THREAD;
}
@@ -346,8 +347,8 @@ static irqreturn_t nvgpu_pci_intr_thread(int irq, void *dev_id)
{
struct gk20a *g = dev_id;
nvgpu_intr_stall_handle(g);
nvgpu_intr_nonstall_handle(g);
nvgpu_cic_intr_stall_handle(g);
nvgpu_cic_intr_nonstall_handle(g);
return IRQ_HANDLED;
}

16
libs/dgpu/libnvgpu-drv-dgpu_safe.export
View File

@@ -529,13 +529,13 @@ nvgpu_ltc_remove_support
nvgpu_ltc_sync_enabled
nvgpu_local_golden_image_get_fault_injection
nvgpu_log_msg_impl
nvgpu_mc_intr_mask
nvgpu_mc_intr_nonstall_pause
nvgpu_mc_intr_nonstall_resume
nvgpu_mc_intr_nonstall_unit_config
nvgpu_mc_intr_stall_pause
nvgpu_mc_intr_stall_resume
nvgpu_mc_intr_stall_unit_config
nvgpu_cic_intr_mask
nvgpu_cic_intr_nonstall_pause
nvgpu_cic_intr_nonstall_resume
nvgpu_cic_intr_nonstall_unit_config
nvgpu_cic_intr_stall_pause
nvgpu_cic_intr_stall_resume
nvgpu_cic_intr_stall_unit_config
nvgpu_mc_reset_dev
nvgpu_mc_reset_devtype
nvgpu_mc_reset_units
@@ -764,7 +764,7 @@ nvgpu_vm_put_buffers
nvgpu_vm_unmap
nvgpu_vmalloc_impl
nvgpu_vzalloc_impl
nvgpu_wait_for_deferred_interrupts
nvgpu_cic_wait_for_deferred_interrupts
nvgpu_worker_deinit
nvgpu_worker_enqueue
nvgpu_worker_init

16
libs/igpu/libnvgpu-drv-igpu_safe.export
View File

@@ -546,13 +546,13 @@ nvgpu_ltc_remove_support
nvgpu_ltc_sync_enabled
nvgpu_local_golden_image_get_fault_injection
nvgpu_log_msg_impl
nvgpu_mc_intr_mask
nvgpu_mc_intr_nonstall_pause
nvgpu_mc_intr_nonstall_resume
nvgpu_mc_intr_nonstall_unit_config
nvgpu_mc_intr_stall_pause
nvgpu_mc_intr_stall_resume
nvgpu_mc_intr_stall_unit_config
nvgpu_cic_intr_mask
nvgpu_cic_intr_nonstall_pause
nvgpu_cic_intr_nonstall_resume
nvgpu_cic_intr_nonstall_unit_config
nvgpu_cic_intr_stall_pause
nvgpu_cic_intr_stall_resume
nvgpu_cic_intr_stall_unit_config
nvgpu_mc_reset_dev
nvgpu_mc_reset_devtype
nvgpu_mc_reset_units
@@ -781,7 +781,7 @@ nvgpu_vm_put_buffers
nvgpu_vm_unmap
nvgpu_vmalloc_impl
nvgpu_vzalloc_impl
nvgpu_wait_for_deferred_interrupts
nvgpu_cic_wait_for_deferred_interrupts
nvgpu_worker_deinit
nvgpu_worker_enqueue
nvgpu_worker_init

4
userspace/units/ce/nvgpu-ce.c
View File

@@ -245,8 +245,8 @@ int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args)
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
val = g->ops.ce.isr_nonstall(g, inst_id, 0);
if (val != (NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_NONSTALL_OPS_POST_EVENTS)) {
if (val != (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_CIC_NONSTALL_OPS_POST_EVENTS)) {
ret = UNIT_FAIL;
unit_err(m, "incorrect ops returned 0x%08x\n", val);
goto done;

67
userspace/units/mc/nvgpu-mc.c
View File

@@ -26,6 +26,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/mc.h>
#include <nvgpu/cic.h>
#include <nvgpu/hal_init.h>
#include <nvgpu/device.h>
#include <nvgpu/engines.h>
@@ -48,27 +49,27 @@
#define ACTIVE_GR_ID 1
#define ACTIVE_CE_ID 2
#define STALL_EN_REG mc_intr_en_set_r(NVGPU_MC_INTR_STALLING)
#define STALL_DIS_REG mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING)
#define NONSTALL_EN_REG mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING)
#define NONSTALL_DIS_REG mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING)
#define STALL_PENDING_REG mc_intr_r(NVGPU_MC_INTR_STALLING)
#define NONSTALL_PENDING_REG mc_intr_r(NVGPU_MC_INTR_NONSTALLING)
#define STALL_EN_REG mc_intr_en_set_r(NVGPU_CIC_INTR_STALLING)
#define STALL_DIS_REG mc_intr_en_clear_r(NVGPU_CIC_INTR_STALLING)
#define NONSTALL_EN_REG mc_intr_en_set_r(NVGPU_CIC_INTR_NONSTALLING)
#define NONSTALL_DIS_REG mc_intr_en_clear_r(NVGPU_CIC_INTR_NONSTALLING)
#define STALL_PENDING_REG mc_intr_r(NVGPU_CIC_INTR_STALLING)
#define NONSTALL_PENDING_REG mc_intr_r(NVGPU_CIC_INTR_NONSTALLING)
struct mc_unit {
u32 num;
u32 bit;
};
static struct mc_unit mc_units[] = {
{ MC_INTR_UNIT_BUS, mc_intr_pbus_pending_f() },
{ MC_INTR_UNIT_PMU, mc_intr_pmu_pending_f() },
{ MC_INTR_UNIT_PRIV_RING, mc_intr_priv_ring_pending_f() },
{ MC_INTR_UNIT_FIFO, mc_intr_pfifo_pending_f() },
{ MC_INTR_UNIT_LTC, mc_intr_ltc_pending_f() },
{ MC_INTR_UNIT_HUB, mc_intr_replayable_fault_pending_f() },
{ MC_INTR_UNIT_GR, (1 << ACTIVE_GR_ID) /* nvgpu_gr_engine_interrupt_mask() */},
{ MC_INTR_UNIT_PMU, mc_intr_pmu_pending_f() },
{ MC_INTR_UNIT_CE, (1 << ACTIVE_CE_ID) /* nvgpu_ce_engine_interrupt_mask() */ },
{ NVGPU_CIC_INTR_UNIT_BUS, mc_intr_pbus_pending_f() },
{ NVGPU_CIC_INTR_UNIT_PMU, mc_intr_pmu_pending_f() },
{ NVGPU_CIC_INTR_UNIT_PRIV_RING, mc_intr_priv_ring_pending_f() },
{ NVGPU_CIC_INTR_UNIT_FIFO, mc_intr_pfifo_pending_f() },
{ NVGPU_CIC_INTR_UNIT_LTC, mc_intr_ltc_pending_f() },
{ NVGPU_CIC_INTR_UNIT_HUB, mc_intr_replayable_fault_pending_f() },
{ NVGPU_CIC_INTR_UNIT_GR, (1 << ACTIVE_GR_ID) /* nvgpu_gr_engine_interrupt_mask() */},
{ NVGPU_CIC_INTR_UNIT_PMU, mc_intr_pmu_pending_f() },
{ NVGPU_CIC_INTR_UNIT_CE, (1 << ACTIVE_CE_ID) /* nvgpu_ce_engine_interrupt_mask() */ },
};
#define NUM_MC_UNITS ARRAY_SIZE(mc_units)
@@ -283,7 +284,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
unit = mc_units[i].num;
/* enable stall intr */
nvgpu_mc_intr_stall_unit_config(g, unit, true);
nvgpu_cic_intr_stall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to enable stall intr for unit %u val=0x%08x\n",
@@ -291,7 +292,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* disable stall intr */
nvgpu_mc_intr_stall_unit_config(g, unit, false);
nvgpu_cic_intr_stall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to disable stall intr for unit %u val=0x%08x\n",
@@ -299,7 +300,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* enable nonstall intr */
nvgpu_mc_intr_nonstall_unit_config(g, unit, true);
nvgpu_cic_intr_nonstall_unit_config(g, unit, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to enable nonstall intr for unit %u val=0x%08x\n",
@@ -307,7 +308,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
}
/* disable stall intr */
nvgpu_mc_intr_nonstall_unit_config(g, unit, false);
nvgpu_cic_intr_nonstall_unit_config(g, unit, false);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != mc_units[i].bit) {
unit_return_fail(m, "failed to disable nonstall intr for unit %u val=0x%08x\n",
@@ -317,7 +318,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* negative testing - invalid unit - stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0); /* clear reg */
nvgpu_mc_intr_stall_unit_config(g, U32_MAX, true);
nvgpu_cic_intr_stall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
@@ -326,7 +327,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args)
/* negative testing - invalid unit - nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0); /* clear reg */
nvgpu_mc_intr_nonstall_unit_config(g, U32_MAX, true);
nvgpu_cic_intr_nonstall_unit_config(g, U32_MAX, true);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != 0U) {
unit_return_fail(m, "Incorrectly enabled interrupt for invalid unit, val=0x%08x\n",
@@ -354,18 +355,18 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
g->mc.intr_mask_restore[1] = 0U;
/* enable something to pause and resume */
nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_PRIV_RING, true);
nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_BUS, true);
nvgpu_cic_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING, true);
nvgpu_cic_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, true);
/* pause stall */
nvgpu_mc_intr_stall_pause(g);
nvgpu_cic_intr_stall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to pause stall intr\n");
}
/* pause nonstall */
nvgpu_mc_intr_nonstall_pause(g);
nvgpu_cic_intr_nonstall_pause(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to pause nonstall intr\n");
@@ -373,7 +374,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* resume stall */
nvgpu_posix_io_writel_reg_space(g, STALL_EN_REG, 0x0);
nvgpu_mc_intr_stall_resume(g);
nvgpu_cic_intr_stall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_EN_REG);
if (val != expected_stall_val) {
unit_return_fail(m, "failed to resume stall intr\n");
@@ -381,7 +382,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* resume nonstall */
nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0);
nvgpu_mc_intr_nonstall_resume(g);
nvgpu_cic_intr_nonstall_resume(g);
val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG);
if (val != expected_nonstall_val) {
unit_return_fail(m, "failed to resume nonstall intr\n");
@@ -392,7 +393,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
nvgpu_posix_io_writel_reg_space(g, NONSTALL_DIS_REG, 0x0);
/* mask all */
nvgpu_mc_intr_mask(g);
nvgpu_cic_intr_mask(g);
val = nvgpu_posix_io_readl_reg_space(g, STALL_DIS_REG);
if (val != U32_MAX) {
unit_return_fail(m, "failed to mask stall intr\n");
@@ -405,7 +406,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args)
/* make this HAL NULL for branch coverage */
save_func = g->ops.mc.intr_mask;
g->ops.mc.intr_mask = NULL;
nvgpu_mc_intr_mask(g);
nvgpu_cic_intr_mask(g);
g->ops.mc.intr_mask = save_func;
return UNIT_SUCCESS;
@@ -448,7 +449,7 @@ int test_is_stall_and_eng_intr_pending(struct unit_module *m, struct gk20a *g,
/* test with everything pending */
for (i = 0U; i < NUM_MC_UNITS; i++) {
intrs_pending |= mc_units[i].bit;
if (mc_units[i].num == MC_INTR_UNIT_GR) {
if (mc_units[i].num == NVGPU_CIC_INTR_UNIT_GR) {
expected_eng_intr_pending = mc_units[i].bit;
}
}
@@ -663,18 +664,18 @@ int test_wait_for_deferred_interrupts(struct unit_module *m, struct gk20a *g,
/* immediate completion */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 0);
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 0);
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
/* cause timeout */
nvgpu_posix_enable_fault_injection(cond_fi, true, 0);
/* wait on stall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_stall_pending, 1);
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
/* wait on nonstall until timeout for branch coverage */
nvgpu_atomic_set(&g->mc.sw_irq_nonstall_pending, 1);
nvgpu_wait_for_deferred_interrupts(g);
nvgpu_cic_wait_for_deferred_interrupts(g);
/* disable the fault injection */
nvgpu_posix_enable_fault_injection(cond_fi, false, 0);

26
userspace/units/mc/nvgpu-mc.h
View File

@@ -74,12 +74,12 @@ int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args);
/**
* Test specification for: test_unit_config
*
* Description: Validate function of nvgpu_mc_intr_stall_unit_config and
* nvgpu_mc_intr_nonstall_unit_config.
* Description: Validate function of nvgpu_cic_intr_stall_unit_config and
* nvgpu_cic_intr_nonstall_unit_config.
*
* Test Type: Feature, Error guessing
*
* Targets: nvgpu_mc_intr_stall_unit_config, nvgpu_mc_intr_nonstall_unit_config,
* Targets: nvgpu_cic_intr_stall_unit_config, nvgpu_cic_intr_nonstall_unit_config,
* mc_gp10b_intr_stall_unit_config, mc_gp10b_intr_nonstall_unit_config
*
* Input: test_mc_setup_env must have been run.
@@ -88,22 +88,22 @@ int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args);
* - Set each of the mock registers for enabling & disabling the stall &
* non-stall interrupts to 0.
* - Loop through table of units:
* - Call nvgpu_mc_intr_stall_unit_config for the unit to enable the stall
* - Call nvgpu_cic_intr_stall_unit_config for the unit to enable the stall
* interrupt.
* - Verify the stall interrupt enable register has the bit set for the unit.
* - Call nvgpu_mc_intr_stall_unit_config for the unit to disable the interrupt.
* - Call nvgpu_cic_intr_stall_unit_config for the unit to disable the interrupt.
* - Verify the stall interrupt disable register has the bit set for the unit.
* - Call nvgpu_mc_intr_nonstall_unit_config for the unit to enable the
* - Call nvgpu_cic_intr_nonstall_unit_config for the unit to enable the
* non-stall interrupt.
* - Verify the non-stall interrupt enable register has the bit set for the unit.
* - Call nvgpu_mc_intr_nonstall_unit_config for the unit to disable the interrupt.
* - Call nvgpu_cic_intr_nonstall_unit_config for the unit to disable the interrupt.
* - Verify the non-stall interrupt disable register has the bit set for the unit.
* - Clear the stall enable register.
* - For negative testing, call nvgpu_mc_intr_stall_unit_config() with an
* - For negative testing, call nvgpu_cic_intr_stall_unit_config() with an
* invalid unit number, and verify no bits are set in the stall interrupt
* enable register.
* - Clear the stall enable register.
* - For negative testing, call nvgpu_mc_intr_nonstall_unit_config() with an
* - For negative testing, call nvgpu_cic_intr_nonstall_unit_config() with an
* invalid unit number, and verify no bits are set in the non-stall interrupt
* enable register.
*
@@ -118,9 +118,9 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: nvgpu_mc_intr_stall_pause, nvgpu_mc_intr_stall_resume,
* nvgpu_mc_intr_nonstall_pause, nvgpu_mc_intr_nonstall_resume,
* nvgpu_mc_intr_mask, mc_gp10b_intr_stall_pause,
* Targets: nvgpu_cic_intr_stall_pause, nvgpu_cic_intr_stall_resume,
* nvgpu_cic_intr_nonstall_pause, nvgpu_cic_intr_nonstall_resume,
* nvgpu_cic_intr_mask, mc_gp10b_intr_stall_pause,
* mc_gp10b_intr_stall_resume, mc_gp10b_intr_nonstall_pause,
* mc_gp10b_intr_nonstall_resume, mc_gp10b_intr_mask
*
@@ -336,7 +336,7 @@ int test_reset_mask(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: nvgpu_wait_for_deferred_interrupts
* Targets: nvgpu_cic_wait_for_deferred_interrupts
*
* Input: test_mc_setup_env must have been run.
*