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gpu: nvgpu: gv100: support clock gating
-Generated list for addr/value pairs using gen_gating_reglist.pl --target_ip=gv100 --soc=t194 -Comment out addresses triggering priv/pbus errors Bug 200399393 Change-Id: Ica0fd65070a7100f20afa32184f4a2e3cad6d0c2 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683101 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
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mobile promotions
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parent
040da8c01d
commit
9fbfffbed0
@@ -264,6 +264,7 @@ nvgpu-y += \
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gv100/nvlink_gv100.o \
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gv100/hal_gv100.o \
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gv100/pmu_gv100.o \
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gv100/gv100_gating_reglist.o \
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pstate/pstate.o \
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clk/clk_vin.o \
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clk/clk_fll.o \
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951
drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c
Normal file
951
drivers/gpu/nvgpu/gv100/gv100_gating_reglist.c
Normal file
@@ -0,0 +1,951 @@
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/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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* This file is autogenerated. Do not edit.
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*/
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#ifndef __gv100_gating_reglist_h__
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#define __gv100_gating_reglist_h__
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#include <linux/types.h>
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#include "gv100_gating_reglist.h"
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struct gating_desc {
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u32 addr;
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u32 prod;
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u32 disable;
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};
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/* slcg bus */
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static const struct gating_desc gv100_slcg_bus[] = {
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{.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
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};
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/* slcg ce2 */
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static const struct gating_desc gv100_slcg_ce2[] = {
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{.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe},
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};
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/* slcg chiplet */
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static const struct gating_desc gv100_slcg_chiplet[] = {
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{.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010c37c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010c47c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010c57c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010d37c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010d47c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010d57c, .prod = 0x00000000, .disable = 0x00000007},
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/* fix priv error */
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/*{.addr = 0x0010d67c, .prod = 0x00000000, .disable = 0x00000007},*/
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/*{.addr = 0x0010d77c, .prod = 0x00000000, .disable = 0x00000007},*/
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{.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
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};
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/* slcg fb */
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static const struct gating_desc gv100_slcg_fb[] = {
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{.addr = 0x00100d14, .prod = 0x00000020, .disable = 0xfffffffe},
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{.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x001facb4, .prod = 0x00000000, .disable = 0x000001fe},
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};
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/* slcg fifo */
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static const struct gating_desc gv100_slcg_fifo[] = {
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{.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe},
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};
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/* slcg gr */
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static const struct gating_desc gv100_slcg_gr[] = {
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{.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe},
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{.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
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{.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe},
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{.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe},
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{.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
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{.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
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{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002},
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{.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
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{.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe},
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{.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
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{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
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{.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe},
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{.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
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{.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},
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{.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe},
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{.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
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{.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
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{.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
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{.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
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{.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff},
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{.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
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{.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
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/* fix priv error */
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/*{.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe},*/
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{.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe},
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{.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe},
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{.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe},
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{.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe},
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{.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e},
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{.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe},
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{.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e},
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{.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e},
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{.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe},
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{.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e},
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{.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e},
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{.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
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{.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
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{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
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{.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x000000ff},
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{.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x000000ff},
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/* fix priv error */
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/*{.addr = 0x00413014, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x00413284, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x004131ac, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x00413224, .prod = 0x00000000, .disable = 0x000000ff},*/
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/*{.addr = 0x00413414, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x00413684, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x004135ac, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x00413624, .prod = 0x00000000, .disable = 0x000000ff},*/
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/*{.addr = 0x00413814, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x00413a84, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x004139ac, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x00413a24, .prod = 0x00000000, .disable = 0x000000ff},*/
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/*{.addr = 0x00413c14, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x00413e84, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x00413dac, .prod = 0x00000000, .disable = 0x0001fffe},*/
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/*{.addr = 0x00413e24, .prod = 0x00000000, .disable = 0x000000ff},*/
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{.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff},
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};
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/* slcg ltc */
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static const struct gating_desc gv100_slcg_ltc[] = {
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{.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0015495c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x00154b5c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0015695c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x00156b5c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe},
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/* fix priv error */
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/*{.addr = 0x00158050, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015855c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015875c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015895c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x00158b5c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015835c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015a050, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015a55c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015a75c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015a95c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015ab5c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015a35c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015c050, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015c55c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015c75c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015c95c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015cb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015c35c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015e050, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015e55c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015e75c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015e95c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015eb5c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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/*{.addr = 0x0015e35c, .prod = 0x00000000, .disable = 0xfffffffe},*/
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{.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
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};
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/* slcg perf */
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static const struct gating_desc gv100_slcg_perf[] = {
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{.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000},
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/* fix priv error */
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/*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/
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/*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/
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{.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246218, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246418, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246618, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246818, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00246a18, .prod = 0xffffffff, .disable = 0x00000000},
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/* fix priv error */
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/*{.addr = 0x00246c18, .prod = 0xffffffff, .disable = 0x00000000},*/
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/*{.addr = 0x00246e18, .prod = 0xffffffff, .disable = 0x00000000},*/
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{.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244218, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244418, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244618, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244818, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x00244a18, .prod = 0xffffffff, .disable = 0x00000000},
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{.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000},
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};
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/* slcg PriRing */
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static const struct gating_desc gv100_slcg_priring[] = {
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{.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
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};
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/* slcg pwr_csb */
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static const struct gating_desc gv100_slcg_pwr_csb[] = {
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{.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe},
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{.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f},
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{.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe},
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{.addr = 0x000016b8, .prod = 0x00000008, .disable = 0x0000000f},
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};
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/* slcg pmu */
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static const struct gating_desc gv100_slcg_pmu[] = {
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{.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
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{.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe},
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{.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
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};
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/* therm gr */
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static const struct gating_desc gv100_slcg_therm[] = {
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{.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f},
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};
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/* slcg Xbar */
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static const struct gating_desc gv100_slcg_xbar[] = {
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{.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe},
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{.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe},
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{.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
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{.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
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{.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe},
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{.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe},
|
||||
{.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe},
|
||||
{.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe},
|
||||
{.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe},
|
||||
};
|
||||
|
||||
/* blcg bus */
|
||||
static const struct gating_desc gv100_blcg_bus[] = {
|
||||
{.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
|
||||
};
|
||||
|
||||
/* blcg ce */
|
||||
static const struct gating_desc gv100_blcg_ce[] = {
|
||||
{.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
};
|
||||
|
||||
/* blcg ctxsw prog */
|
||||
static const struct gating_desc gv100_blcg_ctxsw_prog[] = {
|
||||
};
|
||||
|
||||
/* blcg fb */
|
||||
static const struct gating_desc gv100_blcg_fb[] = {
|
||||
{.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
|
||||
{.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
/* fix priv error */
|
||||
/*{.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},*/
|
||||
{.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
|
||||
{.addr = 0x001facb0, .prod = 0x00004242, .disable = 0x00000000},
|
||||
};
|
||||
|
||||
/* blcg fifo */
|
||||
static const struct gating_desc gv100_blcg_fifo[] = {
|
||||
{.addr = 0x000026e0, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
};
|
||||
|
||||
/* blcg gr */
|
||||
static const struct gating_desc gv100_blcg_gr[] = {
|
||||
{.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
|
||||
{.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
|
||||
{.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
|
||||
{.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
|
||||
{.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
|
||||
{.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
|
||||
{.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
|
||||
{.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
|
||||
{.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
|
||||
{.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000},
|
||||
{.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00419c80, .prod = 0x00004048, .disable = 0x00000000},
|
||||
{.addr = 0x00419c88, .prod = 0x00004048, .disable = 0x00000000},
|
||||
{.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000},
|
||||
{.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000},
|
||||
{.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000},
|
||||
{.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000},
|
||||
{.addr = 0x00419a40, .prod = 0x00000545, .disable = 0x00000000},
|
||||
{.addr = 0x00419a48, .prod = 0x00004545, .disable = 0x00000000},
|
||||
{.addr = 0x00419a50, .prod = 0x00004545, .disable = 0x00000000},
|
||||
{.addr = 0x00419a58, .prod = 0x00004545, .disable = 0x00000000},
|
||||
{.addr = 0x00419a60, .prod = 0x00000505, .disable = 0x00000000},
|
||||
{.addr = 0x00419a68, .prod = 0x00000505, .disable = 0x00000000},
|
||||
{.addr = 0x00419a78, .prod = 0x00000505, .disable = 0x00000000},
|
||||
{.addr = 0x00419a80, .prod = 0x00004545, .disable = 0x00000000},
|
||||
{.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
|
||||
{.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
/* fix priv error */
|
||||
/*{.addr = 0x00413010, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00413280, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x004131a8, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00413410, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00413680, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x004135a8, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00413810, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00413a80, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x004139a8, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00413c10, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00413e80, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00413da8, .prod = 0x0000c242, .disable = 0x00000000},*/
|
||||
{.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
};
|
||||
|
||||
/* blcg ltc */
|
||||
static const struct gating_desc gv100_blcg_ltc[] = {
|
||||
{.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001549e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001549c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x00154be0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x00154bc8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001569e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001569c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x00156be0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x00156bc8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
/* fix priv error */
|
||||
/*{.addr = 0x00158030, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00158040, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x001585e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x001585c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x001587e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x001587c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x001589e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x001589c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00158be0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x00158bc8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x001583e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x001583c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a030, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a040, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a5e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a5c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a7e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a7c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a9e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a9c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015abe0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015abc8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a3e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015a3c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c030, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c040, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c5e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c5c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c7e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c7c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c9e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c9c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015cbe0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015cbc8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c3e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015c3c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e030, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e040, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e5e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e5c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e7e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e7c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e9e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e9c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015ebe0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015ebc8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e3e0, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
/*{.addr = 0x0015e3c8, .prod = 0x00000044, .disable = 0x00000000},*/
|
||||
{.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
};
|
||||
|
||||
/* blcg pwr_csb */
|
||||
static const struct gating_desc gv100_blcg_pwr_csb[] = {
|
||||
{.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000},
|
||||
};
|
||||
|
||||
/* blcg pmu */
|
||||
static const struct gating_desc gv100_blcg_pmu[] = {
|
||||
{.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
|
||||
};
|
||||
|
||||
/* blcg Xbar */
|
||||
static const struct gating_desc gv100_blcg_xbar[] = {
|
||||
{.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000},
|
||||
{.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000},
|
||||
{.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000},
|
||||
{.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000},
|
||||
};
|
||||
|
||||
/* pg gr */
|
||||
static const struct gating_desc gv100_pg_gr[] = {
|
||||
};
|
||||
|
||||
/* inline functions */
|
||||
void gv100_slcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_bus) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_bus[i].addr,
|
||||
gv100_slcg_bus[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_bus[i].addr,
|
||||
gv100_slcg_bus[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_ce2_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_ce2) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_ce2[i].addr,
|
||||
gv100_slcg_ce2[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_ce2[i].addr,
|
||||
gv100_slcg_ce2[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_chiplet) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_chiplet[i].addr,
|
||||
gv100_slcg_chiplet[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_chiplet[i].addr,
|
||||
gv100_slcg_chiplet[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
}
|
||||
|
||||
void gv100_slcg_fb_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_fb) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_fb[i].addr,
|
||||
gv100_slcg_fb[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_fb[i].addr,
|
||||
gv100_slcg_fb[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_fifo_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_fifo) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_fifo[i].addr,
|
||||
gv100_slcg_fifo[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_fifo[i].addr,
|
||||
gv100_slcg_fifo[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_gr) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_gr[i].addr,
|
||||
gv100_slcg_gr[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_gr[i].addr,
|
||||
gv100_slcg_gr[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_ltc) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_ltc[i].addr,
|
||||
gv100_slcg_ltc[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_ltc[i].addr,
|
||||
gv100_slcg_ltc[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_perf_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_perf) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_perf[i].addr,
|
||||
gv100_slcg_perf[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_perf[i].addr,
|
||||
gv100_slcg_perf[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_priring_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_priring) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_priring[i].addr,
|
||||
gv100_slcg_priring[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_priring[i].addr,
|
||||
gv100_slcg_priring[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_pwr_csb) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_pwr_csb[i].addr,
|
||||
gv100_slcg_pwr_csb[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_pwr_csb[i].addr,
|
||||
gv100_slcg_pwr_csb[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_pmu_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_pmu) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_pmu[i].addr,
|
||||
gv100_slcg_pmu[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_pmu[i].addr,
|
||||
gv100_slcg_pmu[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_therm_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_therm) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_therm[i].addr,
|
||||
gv100_slcg_therm[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_therm[i].addr,
|
||||
gv100_slcg_therm[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_slcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_slcg_xbar) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_slcg_xbar[i].addr,
|
||||
gv100_slcg_xbar[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_slcg_xbar[i].addr,
|
||||
gv100_slcg_xbar[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_bus) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_bus[i].addr,
|
||||
gv100_blcg_bus[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_bus[i].addr,
|
||||
gv100_blcg_bus[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_ce_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_ce) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_ce[i].addr,
|
||||
gv100_blcg_ce[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_ce[i].addr,
|
||||
gv100_blcg_ce[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_ctxsw_prog) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr,
|
||||
gv100_blcg_ctxsw_prog[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_ctxsw_prog[i].addr,
|
||||
gv100_blcg_ctxsw_prog[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_fb_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_fb) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_fb[i].addr,
|
||||
gv100_blcg_fb[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_fb[i].addr,
|
||||
gv100_blcg_fb[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_fifo_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_fifo) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_fifo[i].addr,
|
||||
gv100_blcg_fifo[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_fifo[i].addr,
|
||||
gv100_blcg_fifo[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_gr) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_gr[i].addr,
|
||||
gv100_blcg_gr[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_gr[i].addr,
|
||||
gv100_blcg_gr[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_ltc_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_ltc) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_ltc[i].addr,
|
||||
gv100_blcg_ltc[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_ltc[i].addr,
|
||||
gv100_blcg_ltc[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_pwr_csb) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_pwr_csb[i].addr,
|
||||
gv100_blcg_pwr_csb[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_pwr_csb[i].addr,
|
||||
gv100_blcg_pwr_csb[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_pmu_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_pmu) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_pmu[i].addr,
|
||||
gv100_blcg_pmu[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_pmu[i].addr,
|
||||
gv100_blcg_pmu[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gv100_blcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_blcg_xbar) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_blcg_xbar[i].addr,
|
||||
gv100_blcg_xbar[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_blcg_xbar[i].addr,
|
||||
gv100_blcg_xbar[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gv100_pg_gr) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gv100_pg_gr[i].addr,
|
||||
gv100_pg_gr[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gv100_pg_gr[i].addr,
|
||||
gv100_pg_gr[i].disable);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __gv100_gating_reglist_h__ */
|
||||
99
drivers/gpu/nvgpu/gv100/gv100_gating_reglist.h
Normal file
99
drivers/gpu/nvgpu/gv100/gv100_gating_reglist.h
Normal file
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (c) 2018, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "gk20a/gk20a.h"
|
||||
|
||||
void gv100_slcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_ce2_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_chiplet_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_fb_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_fifo_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gr_gv100_slcg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void ltc_gv100_slcg_ltc_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_perf_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_priring_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_pmu_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_therm_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_slcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_ce_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_fb_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_fifo_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_ltc_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_pmu_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gv100_blcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
@@ -82,7 +82,6 @@
|
||||
#include "gv11b/pmu_gv11b.h"
|
||||
#include "gv11b/fifo_gv11b.h"
|
||||
#include "gv11b/regops_gv11b.h"
|
||||
#include "gv11b/gv11b_gating_reglist.h"
|
||||
#include "gv11b/subctx_gv11b.h"
|
||||
|
||||
#include "gv100.h"
|
||||
@@ -98,6 +97,7 @@
|
||||
#include "gv100/pmu_gv100.h"
|
||||
#include "gv100/nvlink_gv100.h"
|
||||
#include "gv100/regops_gv100.h"
|
||||
#include "gv100/gv100_gating_reglist.h"
|
||||
|
||||
#include <nvgpu/bus.h>
|
||||
#include <nvgpu/debug.h>
|
||||
@@ -456,6 +456,56 @@ static const struct gpu_ops gv100_ops = {
|
||||
.init_nvlink = gv100_fb_init_nvlink,
|
||||
.enable_nvlink = gv100_fb_enable_nvlink,
|
||||
},
|
||||
.clock_gating = {
|
||||
.slcg_bus_load_gating_prod =
|
||||
gv100_slcg_bus_load_gating_prod,
|
||||
.slcg_ce2_load_gating_prod =
|
||||
gv100_slcg_ce2_load_gating_prod,
|
||||
.slcg_chiplet_load_gating_prod =
|
||||
gv100_slcg_chiplet_load_gating_prod,
|
||||
.slcg_ctxsw_firmware_load_gating_prod =
|
||||
gv100_slcg_ctxsw_firmware_load_gating_prod,
|
||||
.slcg_fb_load_gating_prod =
|
||||
gv100_slcg_fb_load_gating_prod,
|
||||
.slcg_fifo_load_gating_prod =
|
||||
gv100_slcg_fifo_load_gating_prod,
|
||||
.slcg_gr_load_gating_prod =
|
||||
gr_gv100_slcg_gr_load_gating_prod,
|
||||
.slcg_ltc_load_gating_prod =
|
||||
ltc_gv100_slcg_ltc_load_gating_prod,
|
||||
.slcg_perf_load_gating_prod =
|
||||
gv100_slcg_perf_load_gating_prod,
|
||||
.slcg_priring_load_gating_prod =
|
||||
gv100_slcg_priring_load_gating_prod,
|
||||
.slcg_pmu_load_gating_prod =
|
||||
gv100_slcg_pmu_load_gating_prod,
|
||||
.slcg_therm_load_gating_prod =
|
||||
gv100_slcg_therm_load_gating_prod,
|
||||
.slcg_xbar_load_gating_prod =
|
||||
gv100_slcg_xbar_load_gating_prod,
|
||||
.blcg_bus_load_gating_prod =
|
||||
gv100_blcg_bus_load_gating_prod,
|
||||
.blcg_ce_load_gating_prod =
|
||||
gv100_blcg_ce_load_gating_prod,
|
||||
.blcg_ctxsw_firmware_load_gating_prod =
|
||||
gv100_blcg_ctxsw_firmware_load_gating_prod,
|
||||
.blcg_fb_load_gating_prod =
|
||||
gv100_blcg_fb_load_gating_prod,
|
||||
.blcg_fifo_load_gating_prod =
|
||||
gv100_blcg_fifo_load_gating_prod,
|
||||
.blcg_gr_load_gating_prod =
|
||||
gv100_blcg_gr_load_gating_prod,
|
||||
.blcg_ltc_load_gating_prod =
|
||||
gv100_blcg_ltc_load_gating_prod,
|
||||
.blcg_pwr_csb_load_gating_prod =
|
||||
gv100_blcg_pwr_csb_load_gating_prod,
|
||||
.blcg_pmu_load_gating_prod =
|
||||
gv100_blcg_pmu_load_gating_prod,
|
||||
.blcg_xbar_load_gating_prod =
|
||||
gv100_blcg_xbar_load_gating_prod,
|
||||
.pg_gr_load_gating_prod =
|
||||
gr_gv100_pg_gr_load_gating_prod,
|
||||
},
|
||||
.fifo = {
|
||||
.get_preempt_timeout = gv100_fifo_get_preempt_timeout,
|
||||
.init_fifo_setup_hw = gv11b_init_fifo_setup_hw,
|
||||
|
||||
Reference in New Issue
Block a user