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gpu: nvgpu: add gr.process_context_buffer_priv_segment gops

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1. Add below gr gops to process context buffer's priv segment.
int (*process_context_buffer_priv_segment)(struct gk20a *g,
					 enum ctxsw_addr_type addr_type,
					 u32 pri_addr,
					 u32 gpc_num, u32 num_tpcs,
					 u32 num_ppcs, u32 ppc_mask,
					 u32 *priv_offset);
Update all chips to use gr_gk20a_process_context_buffer_priv_segment()
as new gr hal.
2. Add and use ppc, tpc and etpc count functions to retrieve total count.

Bug 2960720
JIRA NVGPU-5502

Change-Id: I6cec36c323ff49ded853cd5cbfd9e0a28602b8ed
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340372
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2020-05-06 21:51:53 -07:00
committed by Alex Waterman
parent a629b48013
commit a039261724
9 changed files with 69 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/gpu/nvgpu/common/netlist/netlist.c
View File

@@ -886,6 +886,42 @@ struct netlist_aiv_list *nvgpu_netlist_get_perf_pma_control_ctxsw_regs(
{
return &g->netlist_vars->ctxsw_regs.perf_pma_control;
}
u32 nvgpu_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_netlist_get_ppc_ctxsw_regs(g)->count;
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
if (count == 0U) {
count = nvgpu_next_netlist_get_ppc_ctxsw_regs_count(g);
}
#endif
return count;
}
u32 nvgpu_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_netlist_get_tpc_ctxsw_regs(g)->count;
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
if (count == 0U) {
count = nvgpu_next_netlist_get_tpc_ctxsw_regs_count(g);
}
#endif
return count;
}
u32 nvgpu_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_netlist_get_etpc_ctxsw_regs(g)->count;
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
if (count == 0U) {
count = nvgpu_next_netlist_get_etpc_ctxsw_regs_count(g);
}
#endif
return count;
}
#endif /* CONFIG_NVGPU_DEBUGGER */
#ifdef CONFIG_NVGPU_NON_FUSA

16
drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
View File

@@ -970,7 +970,7 @@ static int gr_gk20a_find_priv_offset_in_ext_buffer(struct gk20a *g,
}
static int
int
gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g,
enum ctxsw_addr_type addr_type,
u32 pri_addr,
@@ -1136,19 +1136,19 @@ static int gr_gk20a_determine_ppc_configuration(struct gk20a *g,
u32 *reg_ppc_count)
{
u32 num_pes_per_gpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_PES_PER_GPC);
u32 ppc_count = nvgpu_netlist_get_ppc_ctxsw_regs_count(g);
/*
* if there is only 1 PES_PER_GPC, then we put the PES registers
* in the GPC reglist, so we can't error out if ppc.count == 0
*/
if ((!g->netlist_valid) ||
((nvgpu_netlist_get_ppc_ctxsw_regs(g)->count == 0U) &&
(num_pes_per_gpc > 1U))) {
((ppc_count == 0U) && (num_pes_per_gpc > 1U))) {
return -EINVAL;
}
g->ops.gr.ctxsw_prog.get_ppc_info(context, num_ppcs, ppc_mask);
*reg_ppc_count = nvgpu_netlist_get_ppc_ctxsw_regs(g)->count;
*reg_ppc_count = ppc_count;
return 0;
}
@@ -1161,8 +1161,8 @@ int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g,
u32 *__offset_in_segment)
{
u32 offset_in_segment = 0;
u32 tpc_count = nvgpu_netlist_get_tpc_ctxsw_regs(g)->count;
u32 etpc_count = nvgpu_netlist_get_etpc_ctxsw_regs(g)->count;
u32 tpc_count = nvgpu_netlist_get_tpc_ctxsw_regs_count(g);
u32 etpc_count = nvgpu_netlist_get_etpc_ctxsw_regs_count(g);
if (addr_type == CTXSW_ADDR_TYPE_TPC) {
/*
@@ -1283,7 +1283,7 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
/* Find the offset in the FECS segment. */
offset_to_segment = sys_priv_offset * 256U;
err = gr_gk20a_process_context_buffer_priv_segment(g,
err = g->ops.gr.process_context_buffer_priv_segment(g,
addr_type, addr,
0, 0, 0, 0,
&offset);
@@ -1352,7 +1352,7 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
"offset_to_segment 0x%#08x",
offset_to_segment);
err = gr_gk20a_process_context_buffer_priv_segment(g,
err = g->ops.gr.process_context_buffer_priv_segment(g,
addr_type, addr,
i, num_tpcs,
num_ppcs, ppc_mask,

9
drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h
View File

@@ -1,7 +1,7 @@
/*
* GK20A Graphics Engine
*
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -104,6 +104,13 @@ void gr_gk20a_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr,
int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g,
enum ctxsw_addr_type addr_type, u32 num_tpcs, u32 num_ppcs,
u32 reg_list_ppc_count, u32 *__offset_in_segment);
int
gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g,
enum ctxsw_addr_type addr_type,
u32 pri_addr,
u32 gpc_num, u32 num_tpcs,
u32 num_ppcs, u32 ppc_mask,
u32 *priv_offset);
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif /*__GR_GK20A_H__*/

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -236,6 +236,8 @@ static const struct gpu_ops gm20b_ops = {
.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
.get_offset_in_gpccs_segment =
gr_gk20a_get_offset_in_gpccs_segment,
.process_context_buffer_priv_segment =
gr_gk20a_process_context_buffer_priv_segment,
.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
.set_debug_mode = gm20b_gr_set_debug_mode,
.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -289,6 +289,8 @@ static const struct gpu_ops gp10b_ops = {
.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
.get_offset_in_gpccs_segment =
gr_gk20a_get_offset_in_gpccs_segment,
.process_context_buffer_priv_segment =
gr_gk20a_process_context_buffer_priv_segment,
.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
.set_debug_mode = gm20b_gr_set_debug_mode,
.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -365,6 +365,8 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
.get_offset_in_gpccs_segment =
gr_gk20a_get_offset_in_gpccs_segment,
.process_context_buffer_priv_segment =
gr_gk20a_process_context_buffer_priv_segment,
.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
.set_debug_mode = gm20b_gr_set_debug_mode,
.set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode,

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -403,6 +403,8 @@ static const struct gpu_ops tu104_ops = {
.split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr,
.get_offset_in_gpccs_segment =
gr_tu104_get_offset_in_gpccs_segment,
.process_context_buffer_priv_segment =
gr_gk20a_process_context_buffer_priv_segment,
.get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets,
.set_debug_mode = gm20b_gr_set_debug_mode,
.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,

6
drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
View File

@@ -1184,6 +1184,12 @@ struct gops_gr {
u32 *offsets, u32 *offset_addrs,
u32 *num_offsets,
bool is_quad, u32 quad);
int (*process_context_buffer_priv_segment)(struct gk20a *g,
enum ctxsw_addr_type addr_type,
u32 pri_addr,
u32 gpc_num, u32 num_tpcs,
u32 num_ppcs, u32 ppc_mask,
u32 *priv_offset);
void (*set_debug_mode)(struct gk20a *g, bool enable);
int (*set_mmu_debug_mode)(struct gk20a *g,
struct nvgpu_channel *ch, bool enable);

3
drivers/gpu/nvgpu/include/nvgpu/netlist.h
View File

@@ -388,6 +388,9 @@ struct netlist_aiv_list *nvgpu_netlist_get_perf_gpc_control_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_netlist_get_perf_pma_control_ctxsw_regs(
struct gk20a *g);
u32 nvgpu_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g);
u32 nvgpu_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g);
u32 nvgpu_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g);
#endif /* CONFIG_NVGPU_DEBUGGER */
#ifdef CONFIG_NVGPU_NON_FUSA