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gpu: nvgpu: log mask for multimedia engines

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Introducing gpu_dbg_mme for multimedia debug prints.

Jira NVGPU-9429
Bug 3962979

Change-Id: I9c84c9336a10af864f61d314dc811d038d1d2d87
Signed-off-by: Santosh BS <santoshb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2908237
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Santosh BS
2023-05-22 07:35:21 +00:00
committed by mobile promotions
parent 3207a29fd7
commit a062676e71
3 changed files with 13 additions and 9 deletions
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10
drivers/gpu/nvgpu/common/multimedia/multimedia.c
View File

@@ -205,7 +205,7 @@ int nvgpu_multimedia_copy_fw(struct gk20a *g, const char *fw_name, u32 *ucode_he
void *ucode = NULL;
int err = 0;
nvgpu_log(g, gpu_dbg_info, "Loading the firmware: %s", fw_name);
nvgpu_log(g, gpu_dbg_mme, "Loading the firmware: %s", fw_name);
multimedia_fw = nvgpu_request_firmware(g, fw_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
@@ -219,19 +219,19 @@ int nvgpu_multimedia_copy_fw(struct gk20a *g, const char *fw_name, u32 *ucode_he
MULTIMEDIA_UCODE_HEADER_SIZE_BYTES);
ucode = multimedia_fw->data + fw_hdr->data_offset;
nvgpu_log(g, gpu_dbg_info, "firmware header: magic= 0x%x ver= 0x%x size= 0x%x",
nvgpu_log(g, gpu_dbg_mme, "firmware header: magic= 0x%x ver= 0x%x size= 0x%x",
fw_hdr->fw_magic,
fw_hdr->fw_ver,
fw_hdr->fw_size);
nvgpu_log(g, gpu_dbg_info, "firmware header: ucode header offset= 0x%x, "
nvgpu_log(g, gpu_dbg_mme, "firmware header: ucode header offset= 0x%x, "
"data (offset,size): 0x%x 0x%x",
fw_hdr->header_offset,
fw_hdr->data_offset,
fw_hdr->data_size);
nvgpu_log(g, gpu_dbg_info, "ucode header: code (offset,size): 0x%x, 0x%x",
nvgpu_log(g, gpu_dbg_mme, "ucode header: code (offset,size): 0x%x, 0x%x",
ucode_header[OS_CODE_OFFSET],
ucode_header[OS_CODE_SIZE]);
nvgpu_log(g, gpu_dbg_info, "ucode header: data (offset,size): 0x%x, 0x%x",
nvgpu_log(g, gpu_dbg_mme, "ucode header: data (offset,size): 0x%x, 0x%x",
ucode_header[OS_DATA_OFFSET],
ucode_header[OS_DATA_SIZE]);

7
drivers/gpu/nvgpu/common/multimedia/nvenc.c
View File

@@ -96,7 +96,7 @@ int nvgpu_nvenc_falcon_boot(struct gk20a *g)
struct nvgpu_mem *nvenc_mem_desc = &nvenc->nvenc_mem_desc;
u32 *ucode_header = nvenc->ucode_header;
nvgpu_log_fn(g, " ");
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_mme, " ");
/* Reset nvenc HW unit */
err = nvgpu_mc_reset_units(g, NVGPU_UNIT_NVENC);
@@ -142,7 +142,8 @@ int nvgpu_nvenc_falcon_boot(struct gk20a *g)
err = -ETIMEDOUT;
}
nvgpu_log(g, gpu_dbg_info, "NVENC NS boot %s!", err ? "SUCCESS" : "FAILED");
nvgpu_log(g, gpu_dbg_info | gpu_dbg_mme,
"NVENC NS boot %s!", err ? "SUCCESS" : "FAILED");
done:
return err;
@@ -152,6 +153,8 @@ int nvgpu_nvenc_reset(struct gk20a *g)
{
int err = 0;
nvgpu_log(g, gpu_dbg_info | gpu_dbg_mme, "Resetting nvenc");
if (g->ops.nvenc.halt_engine != NULL) {
g->ops.nvenc.halt_engine(g);
}

5
drivers/gpu/nvgpu/include/nvgpu/log_common.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -88,5 +88,6 @@ enum nvgpu_log_type {
#define gpu_dbg_nvs BIT(45) /* NvGPU's NVS logging. */
#define gpu_dbg_nvs_internal BIT(46) /* Internal NVS logging. */
#endif
#define gpu_dbg_gsp BIT(47) /* GSP Scheduler debugging */
#define gpu_dbg_gsp BIT(47) /* GSP Scheduler debugging */
#define gpu_dbg_mme BIT(48) /* Multimedia Engines debugging */
#endif