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gpu: nvgpu: move gv100 ACR functions to gv11b

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moved some gv100 ACR functions to gv11b as gv11b will be used for
safety build & gv11b dependency on gv100 will removed with this
changes to compile out gv100 ACR files from safety build.

LS-PMU ACR related functions put under NVGPU_LS_PMU check
to compile out those functions for safety-build

JIRA NVGPU-3418

Change-Id: I1af29c649e8ef7f46e369f00245efe93a55d1658
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123739
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-05-22 22:10:36 +05:30
committed by mobile promotions
parent 47dc0b9ebd
commit a081fba30c
5 changed files with 52 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c
View File

@@ -39,6 +39,7 @@ static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value)
dma_addr->hi |= u64_hi32(value);
}
#ifdef NVGPU_LS_PMU
int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
{
struct lsf_ucode_desc_v1 *lsf_desc;
@@ -74,6 +75,7 @@ int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
exit:
return err;
}
#endif
int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
{

45
drivers/gpu/nvgpu/common/acr/acr_sw_gv100.c
View File

@@ -33,12 +33,7 @@
#include "acr_blob_alloc.h"
#include "acr_bootstrap.h"
#include "acr_blob_construct_v1.h"
static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value)
{
dma_addr->lo |= u64_lo32(value);
dma_addr->hi |= u64_hi32(value);
}
#include "acr_sw_gv11b.h"
static void gv100_acr_patch_wpr_info_to_ucode(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
@@ -90,39 +85,6 @@ static void gv100_acr_patch_wpr_info_to_ucode(struct gk20a *g,
U32(tmp_addr);
}
void gv100_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header)
{
struct nvgpu_mem *acr_ucode_mem = &acr_desc->acr_ucode;
struct flcn_bl_dmem_desc_v1 *bl_dmem_desc =
&acr_desc->bl_dmem_desc_v1;
nvgpu_log_fn(g, " ");
(void) memset(bl_dmem_desc, 0, sizeof(struct flcn_bl_dmem_desc_v1));
bl_dmem_desc->signature[0] = 0U;
bl_dmem_desc->signature[1] = 0U;
bl_dmem_desc->signature[2] = 0U;
bl_dmem_desc->signature[3] = 0U;
bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
flcn64_set_dma(&bl_dmem_desc->code_dma_base,
acr_ucode_mem->gpu_va);
bl_dmem_desc->non_sec_code_off = acr_ucode_header[0U];
bl_dmem_desc->non_sec_code_size = acr_ucode_header[1U];
bl_dmem_desc->sec_code_off = acr_ucode_header[5U];
bl_dmem_desc->sec_code_size = acr_ucode_header[6U];
bl_dmem_desc->code_entry_point = 0U;
flcn64_set_dma(&bl_dmem_desc->data_dma_base,
acr_ucode_mem->gpu_va + acr_ucode_header[2U]);
bl_dmem_desc->data_size = acr_ucode_header[3U];
}
/* LSF init */
static u32 gv100_acr_lsf_pmu(struct gk20a *g,
struct acr_lsf_config *lsf)
@@ -132,7 +94,9 @@ static u32 gv100_acr_lsf_pmu(struct gk20a *g,
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = false;
lsf->is_priv_load = false;
#ifdef NVGPU_LS_PMU
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details_v1;
#endif
lsf->get_cmd_line_args_offset = nvgpu_pmu_fw_get_cmd_line_args_offset;
return BIT32(lsf->falcon_id);
@@ -170,7 +134,6 @@ static u32 gv100_acr_lsf_conifg(struct gk20a *g,
struct nvgpu_acr *acr)
{
u32 lsf_enable_mask = 0;
lsf_enable_mask |= gv100_acr_lsf_pmu(g, &acr->lsf[FALCON_ID_PMU]);
lsf_enable_mask |= gv100_acr_lsf_fecs(g, &acr->lsf[FALCON_ID_FECS]);
lsf_enable_mask |= gv100_acr_lsf_gpccs(g, &acr->lsf[FALCON_ID_GPCCS]);
@@ -216,5 +179,5 @@ void nvgpu_gv100_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
acr->bootstrap_hs_acr = nvgpu_acr_bootstrap_hs_ucode;
acr->patch_wpr_info_to_ucode =
gv100_acr_patch_wpr_info_to_ucode;
acr->acr_fill_bl_dmem_desc = gv100_acr_fill_bl_dmem_desc;
acr->acr_fill_bl_dmem_desc = gv11b_acr_fill_bl_dmem_desc;
}

3
drivers/gpu/nvgpu/common/acr/acr_sw_gv100.h
View File

@@ -29,9 +29,6 @@ struct gk20a;
struct nvgpu_acr;
struct hs_acr;
void gv100_acr_fill_bl_dmem_desc(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, u32 *acr_ucode_header);
void nvgpu_gv100_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
#endif /* ACR_SW_GV100_H */

48
drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c
View File

@@ -31,10 +31,14 @@
#include "acr_blob_alloc.h"
#include "acr_blob_construct_v1.h"
#include "acr_bootstrap.h"
#include "acr_sw_gm20b.h"
#include "acr_sw_gv100.h"
#include "acr_sw_gv11b.h"
static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value)
{
dma_addr->lo |= u64_lo32(value);
dma_addr->hi |= u64_hi32(value);
}
static void gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery)
{
@@ -78,7 +82,41 @@ static void gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
}
}
void gv11b_acr_fill_bl_dmem_desc(struct gk20a *g,
struct nvgpu_acr *acr, struct hs_acr *acr_desc,
u32 *acr_ucode_header)
{
struct nvgpu_mem *acr_ucode_mem = &acr_desc->acr_ucode;
struct flcn_bl_dmem_desc_v1 *bl_dmem_desc =
&acr_desc->bl_dmem_desc_v1;
nvgpu_log_fn(g, " ");
(void) memset(bl_dmem_desc, 0, sizeof(struct flcn_bl_dmem_desc_v1));
bl_dmem_desc->signature[0] = 0U;
bl_dmem_desc->signature[1] = 0U;
bl_dmem_desc->signature[2] = 0U;
bl_dmem_desc->signature[3] = 0U;
bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT;
flcn64_set_dma(&bl_dmem_desc->code_dma_base,
acr_ucode_mem->gpu_va);
bl_dmem_desc->non_sec_code_off = acr_ucode_header[0U];
bl_dmem_desc->non_sec_code_size = acr_ucode_header[1U];
bl_dmem_desc->sec_code_off = acr_ucode_header[5U];
bl_dmem_desc->sec_code_size = acr_ucode_header[6U];
bl_dmem_desc->code_entry_point = 0U;
flcn64_set_dma(&bl_dmem_desc->data_dma_base,
acr_ucode_mem->gpu_va + acr_ucode_header[2U]);
bl_dmem_desc->data_size = acr_ucode_header[3U];
}
/* LSF static config functions */
#ifdef NVGPU_LS_PMU
static u32 gv11b_acr_lsf_pmu(struct gk20a *g,
struct acr_lsf_config *lsf)
{
@@ -97,6 +135,7 @@ static u32 gv11b_acr_lsf_pmu(struct gk20a *g,
return BIT32(lsf->falcon_id);
}
#endif
/* LSF init */
static u32 gv11b_acr_lsf_fecs(struct gk20a *g,
@@ -139,8 +178,9 @@ static u32 gv11b_acr_lsf_conifg(struct gk20a *g,
struct nvgpu_acr *acr)
{
u32 lsf_enable_mask = 0;
#ifdef NVGPU_LS_PMU
lsf_enable_mask |= gv11b_acr_lsf_pmu(g, &acr->lsf[FALCON_ID_PMU]);
#endif
lsf_enable_mask |= gv11b_acr_lsf_fecs(g, &acr->lsf[FALCON_ID_FECS]);
lsf_enable_mask |= gv11b_acr_lsf_gpccs(g, &acr->lsf[FALCON_ID_GPCCS]);
@@ -187,5 +227,5 @@ void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_sys;
acr->bootstrap_hs_acr = nvgpu_acr_bootstrap_hs_ucode;
acr->patch_wpr_info_to_ucode = gv11b_acr_patch_wpr_info_to_ucode;
acr->acr_fill_bl_dmem_desc = gv100_acr_fill_bl_dmem_desc;
acr->acr_fill_bl_dmem_desc = gv11b_acr_fill_bl_dmem_desc;
}

2
drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.h
View File

@@ -26,6 +26,8 @@
struct gk20a;
struct nvgpu_acr;
void gv11b_acr_fill_bl_dmem_desc(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc, u32 *acr_ucode_header);
void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
#endif /* ACR_SW_GV11B_H */