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gpu: nvgpu: add priv lockdown release check for NVRISCV pmu

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IRQ register access will cause priv errors if they
are accessed before priv lockdown is released.
This change adds a polling loop to check priv lockdown
before proceeding further while booting NVRISCV pmu.

Bug 200709761

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I44b8ce4c59b5a9f20901e5ce08610d17725da779
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512351
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Ramesh Mylavarapu
2021-04-09 00:12:59 +05:30
committed by mobile promotions
parent 4d3a935b1a
commit a0b1b3f2be
2 changed files with 55 additions and 1 deletions
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5
drivers/gpu/nvgpu/include/nvgpu/gops/falcon.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,6 +53,9 @@ struct gops_falcon {
void (*set_bcr)(struct nvgpu_falcon *flcn);
void (*dump_brom_stats)(struct nvgpu_falcon *flcn);
u32 (*get_brom_retcode)(struct nvgpu_falcon *flcn);
#if defined(CONFIG_NVGPU_NEXT)
bool (*is_priv_lockdown)(struct nvgpu_falcon *flcn);
#endif
u32 (*dmemc_blk_mask)(void);
bool (*check_brom_passed)(u32 retcode);
void (*brom_config)(struct nvgpu_falcon *flcn, u64 fmc_code_addr,