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gpu: nvgpu: define P-state as a platform variable
move P-state enabling from chip level to platform level. Bug 200559157 Change-Id: Ie71dc801583678dc3a19f2a8438e477e46053591 Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2223300 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
Alex Waterman
parent
a9bb95f859
commit
a12c627574
@@ -1205,7 +1205,6 @@ int gm20b_init_hal(struct gk20a *g)
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gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
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gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
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nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
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nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
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nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
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#ifdef CONFIG_NVGPU_FECS_TRACE
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#ifdef CONFIG_NVGPU_FECS_TRACE
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);
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@@ -1292,7 +1292,6 @@ int gp10b_init_hal(struct gk20a *g)
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gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
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gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
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nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
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nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
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nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
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#ifdef CONFIG_NVGPU_FECS_TRACE
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#ifdef CONFIG_NVGPU_FECS_TRACE
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);
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@@ -1677,9 +1677,6 @@ int tu104_init_hal(struct gk20a *g)
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nvgpu_gr_falcon_load_ctxsw_ucode;
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nvgpu_gr_falcon_load_ctxsw_ucode;
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#endif
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#endif
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/* Disable pmu pstate, as there is no pmu support */
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nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
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nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP,
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nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP,
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false);
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false);
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/* Disable fb mem_unlock */
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/* Disable fb mem_unlock */
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@@ -1694,7 +1691,6 @@ int tu104_init_hal(struct gk20a *g)
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} else
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} else
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#endif
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#endif
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{
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{
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nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
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nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
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nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
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}
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}
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@@ -206,6 +206,14 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
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}
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}
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nvgpu_set_enabled(g, NVGPU_SUPPORT_ASPM, !platform->disable_aspm);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_ASPM, !platform->disable_aspm);
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#ifdef CONFIG_NVGPU_SIM
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
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} else
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#endif
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{
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nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, platform->pstate);
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}
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}
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}
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static void nvgpu_init_vbios_vars(struct gk20a *g)
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static void nvgpu_init_vbios_vars(struct gk20a *g)
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@@ -95,6 +95,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.can_elcg = false,
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.can_elcg = false,
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.disable_aspm = true,
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.disable_aspm = true,
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.pstate = true,
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/* power management callbacks */
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/* power management callbacks */
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.is_railgated = nvgpu_pci_tegra_is_railgated,
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.is_railgated = nvgpu_pci_tegra_is_railgated,
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@@ -136,6 +137,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
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.can_elcg = false,
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.can_elcg = false,
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.disable_aspm = true,
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.disable_aspm = true,
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.pstate = true,
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/* power management callbacks */
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/* power management callbacks */
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.is_railgated = nvgpu_pci_tegra_is_railgated,
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.is_railgated = nvgpu_pci_tegra_is_railgated,
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@@ -85,6 +85,9 @@ struct gk20a_platform {
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/* Set if the platform can unify the small/large address spaces. */
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/* Set if the platform can unify the small/large address spaces. */
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bool unify_address_spaces;
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bool unify_address_spaces;
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/* P-state */
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bool pstate;
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/* Clock configuration is stored here. Platform probe is responsible
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/* Clock configuration is stored here. Platform probe is responsible
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* for filling this data. */
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* for filling this data. */
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struct clk *clk[GK20A_CLKS_MAX];
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struct clk *clk[GK20A_CLKS_MAX];
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