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gpu: nvgpu: define P-state as a platform variable

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move P-state enabling from chip level to platform level.

Bug 200559157

Change-Id: Ie71dc801583678dc3a19f2a8438e477e46053591
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2223300
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Preetham Chandru Ramchandra
2019-10-25 16:10:21 +05:30
committed by Alex Waterman
parent a9bb95f859
commit a12c627574
6 changed files with 13 additions and 6 deletions
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1
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
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@@ -1205,7 +1205,6 @@ int gm20b_init_hal(struct gk20a *g)
gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup; gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
#ifdef CONFIG_NVGPU_FECS_TRACE #ifdef CONFIG_NVGPU_FECS_TRACE
nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);

1
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
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@@ -1292,7 +1292,6 @@ int gp10b_init_hal(struct gk20a *g)
gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup; gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
#ifdef CONFIG_NVGPU_FECS_TRACE #ifdef CONFIG_NVGPU_FECS_TRACE
nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false);
nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false);

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
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@@ -1677,9 +1677,6 @@ int tu104_init_hal(struct gk20a *g)
nvgpu_gr_falcon_load_ctxsw_ucode; nvgpu_gr_falcon_load_ctxsw_ucode;
#endif #endif
/* Disable pmu pstate, as there is no pmu support */
nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP,
false); false);
/* Disable fb mem_unlock */ /* Disable fb mem_unlock */
@@ -1694,7 +1691,6 @@ int tu104_init_hal(struct gk20a *g)
} else } else
#endif #endif
{ {
nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true);
nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
} }

8
drivers/gpu/nvgpu/os/linux/driver_common.c
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@@ -206,6 +206,14 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
} }
nvgpu_set_enabled(g, NVGPU_SUPPORT_ASPM, !platform->disable_aspm); nvgpu_set_enabled(g, NVGPU_SUPPORT_ASPM, !platform->disable_aspm);
#ifdef CONFIG_NVGPU_SIM
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
} else
#endif
{
nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, platform->pstate);
}
} }
static void nvgpu_init_vbios_vars(struct gk20a *g) static void nvgpu_init_vbios_vars(struct gk20a *g)

2
drivers/gpu/nvgpu/os/linux/pci.c
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@@ -95,6 +95,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_elcg = false, .can_elcg = false,
.disable_aspm = true, .disable_aspm = true,
.pstate = true,
/* power management callbacks */ /* power management callbacks */
.is_railgated = nvgpu_pci_tegra_is_railgated, .is_railgated = nvgpu_pci_tegra_is_railgated,
@@ -136,6 +137,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
.can_elcg = false, .can_elcg = false,
.disable_aspm = true, .disable_aspm = true,
.pstate = true,
/* power management callbacks */ /* power management callbacks */
.is_railgated = nvgpu_pci_tegra_is_railgated, .is_railgated = nvgpu_pci_tegra_is_railgated,

3
drivers/gpu/nvgpu/os/linux/platform_gk20a.h
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@@ -85,6 +85,9 @@ struct gk20a_platform {
/* Set if the platform can unify the small/large address spaces. */ /* Set if the platform can unify the small/large address spaces. */
bool unify_address_spaces; bool unify_address_spaces;
/* P-state */
bool pstate;
/* Clock configuration is stored here. Platform probe is responsible /* Clock configuration is stored here. Platform probe is responsible
* for filling this data. */ * for filling this data. */
struct clk *clk[GK20A_CLKS_MAX]; struct clk *clk[GK20A_CLKS_MAX];