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gpu: nvgpu: falcon: address code inspection gaps

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Address following issues uncovered during inspection:
1. Change the comments in struct nvgpu_falcon to doxygen style.
2. Update function description of wait_idle and scrub_wait to
   describe the timeout type.
3. Add more detail to copy_to_imem|dmem.
4. Change constants defined using macros to const u32.

JIRA NVGPU-4787

Change-Id: I88c789a9cf8c20d62a7ad231a6364376c999b8c9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2286522
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Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2020-01-28 19:19:33 +05:30
committed by Alex Waterman
parent c8050eabec
commit a13a9bdf4c
2 changed files with 26 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -33,13 +33,6 @@
#include "nvgpu_next_gpuid.h"
#endif
/* Delay depends on memory size and pwr_clk
* delay = (MAX {IMEM_SIZE, DMEM_SIZE} * 64 + 1) / pwr_clk
* Timeout set is 1msec & status check at interval 10usec
*/
#define MEM_SCRUBBING_TIMEOUT_MAX 1000
#define MEM_SCRUBBING_TIMEOUT_DEFAULT 10
static bool is_falcon_valid(struct nvgpu_falcon *flcn)
{
if (flcn == NULL) {
@@ -148,6 +141,13 @@ int nvgpu_falcon_wait_idle(struct nvgpu_falcon *flcn)
int nvgpu_falcon_mem_scrub_wait(struct nvgpu_falcon *flcn)
{
struct nvgpu_timeout timeout;
/**
* Delay depends on memory size and pwr_clk
* delay = (MAX {IMEM_SIZE, DMEM_SIZE} * 64 + 1) / pwr_clk
* Timeout set is 1msec & status check at interval 10usec
*/
const u32 mem_scrubbing_max_timeout = 1000U;
const u32 mem_scrubbing_default_timeout = 10U;
struct gk20a *g;
int status;
@@ -159,8 +159,8 @@ int nvgpu_falcon_mem_scrub_wait(struct nvgpu_falcon *flcn)
/* check IMEM/DMEM scrubbing complete status */
status = nvgpu_timeout_init(g, &timeout,
MEM_SCRUBBING_TIMEOUT_MAX /
MEM_SCRUBBING_TIMEOUT_DEFAULT,
mem_scrubbing_max_timeout /
mem_scrubbing_default_timeout,
NVGPU_TIMER_RETRY_TIMER);
if (status != 0) {
return status;
@@ -170,7 +170,7 @@ int nvgpu_falcon_mem_scrub_wait(struct nvgpu_falcon *flcn)
if (g->ops.falcon.is_falcon_scrubbing_done(flcn)) {
break;
}
nvgpu_udelay(MEM_SCRUBBING_TIMEOUT_DEFAULT);
nvgpu_udelay(mem_scrubbing_default_timeout);
} while (nvgpu_timeout_expired(&timeout) == 0);
if (nvgpu_timeout_peek_expired(&timeout)) {

30
drivers/gpu/nvgpu/include/nvgpu/falcon.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -215,21 +215,21 @@ struct nvgpu_falcon {
u32 flcn_id;
/** Base address to access falcon registers */
u32 flcn_base;
/* Indicates if the falcon is supported and initialized for use. */
/** Indicates if the falcon is supported and initialized for use. */
bool is_falcon_supported;
/* Indicates if the falcon interrupts are enabled. */
/** Indicates if the falcon interrupts are enabled. */
bool is_interrupt_enabled;
/* Lock to access the falcon's IMEM. */
/** Lock to access the falcon's IMEM. */
struct nvgpu_mutex imem_lock;
/* Lock to access the falcon's DMEM. */
/** Lock to access the falcon's DMEM. */
struct nvgpu_mutex dmem_lock;
#ifdef CONFIG_NVGPU_DGPU
/* Indicates if the falcon supports EMEM. */
/** Indicates if the falcon supports EMEM. */
bool emem_supported;
/* Lock to access the falcon's EMEM. */
/** Lock to access the falcon's EMEM. */
struct nvgpu_mutex emem_lock;
#endif
/* Functions for engine specific reset and memory access. */
/** Functions for engine specific reset and memory access. */
struct nvgpu_falcon_engine_dependency_ops flcn_engine_dep_ops;
};
@@ -289,8 +289,9 @@ int nvgpu_falcon_wait_for_halt(struct nvgpu_falcon *flcn, unsigned int timeout);
* Steps:
* - Validate that the passed in falcon struct is not NULL and is for supported
* falcon. If not valid, return -EINVAL.
* - Initialize the timer using function #nvgpu_timeout_init with duration of
* 2ms. Verify the timeout initialization and return error if failed.
* - Initialize the timer using function #nvgpu_timeout_init with the duration
* of minimum of 200ms in the form of #NVGPU_TIMER_RETRY_TIMER. Verify the
* timeout initialization and return error if failed.
* - While the timeout is not expired, check the falcon units' idle status
* from idlestate register every 100-200us.
* - Return value based on timeout expiry.
@@ -310,8 +311,9 @@ int nvgpu_falcon_wait_idle(struct nvgpu_falcon *flcn);
* Steps:
* - Validate that the passed in falcon struct is not NULL and is for supported
* falcon. If not valid, return -EINVAL.
* - Initialize the timer using function #nvgpu_timeout_init with duration of
* 1ms. Verify the timeout initialization and return error if failed.
* - Initialize the timer using function #nvgpu_timeout_init with the duration
* of minimum of 1ms in the form of #NVGPU_TIMER_RETRY_TIMER. Verify the
* timeout initialization and return error if failed.
* - While the timeout is not expired, check the falcon memory scrubbing status
* from dmactrl register every 10us.
* - Return value based on timeout expiry.
@@ -349,7 +351,7 @@ int nvgpu_falcon_mem_scrub_wait(struct nvgpu_falcon *flcn);
* - Copy data \a src of \a size though \a port at offset \a dst of DMEM.
* - Set \a dst offset and AINCW (auto increment on write) bit in DMEMC
* (control) register corresponding to the port \a port.
* - Write the data words from \a src to DMEMD (data) register.
* - Write the data words from \a src to DMEMD (data) register word-by-word.
* - Write the remaining bytes to DMEMD register zeroing non-data bytes.
* - Read the DMEMC register and verify the count of bytes written.
* - Release DMEM copy lock.
@@ -390,7 +392,7 @@ int nvgpu_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
* - Set \a dst offset and AINCW (auto increment on write) bit in IMEMC
* (control) register corresponding to the port \a port. Set the secure
* bit based on \a sec.
* - Write the data words from \a src to IMEMD (data) register.
* - Write the data words from \a src to IMEMD (data) register word-by-word.
* - Write \a tag every 256B (64 words). Increment the tag.
* - Zero the remaining bytes in the last 256B block (if total size is
* not multiple of 256B block) by writing zero to IMEMD register.