gpu: nvgpu: ltc: move chip specific files to hal

Move ltc chip speciifc files to hal from common

JIRA NVGPU-2044

Change-Id: If3f5e77fce1dfa94336e1be616833cef5b91839b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070186
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c

@@ -0,0 +1,352 @@
+/*
+ * GM20B L2
+ *
+ * Copyright (c) 2014-2019 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <trace/events/gk20a.h>
+
+#include <nvgpu/timers.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/ltc.h>
+#include <nvgpu/io.h>
+#include <nvgpu/utils.h>
+#include <nvgpu/gk20a.h>
+
+#include <nvgpu/hw/gm20b/hw_ltc_gm20b.h>
+#include <nvgpu/hw/gm20b/hw_top_gm20b.h>
+#include <nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h>
+
+#include "ltc_gm20b.h"
+
+void gm20b_ltc_init_fs_state(struct gk20a *g)
+{
+	u32 reg;
+
+	nvgpu_log_info(g, "initialize gm20b l2");
+
+	g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r());
+	g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r());
+	nvgpu_log_info(g, "%d ltcs out of %d", g->ltc_count, g->max_ltc_count);
+
+	reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r());
+	g->slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(reg);;
+	g->cacheline_size =
+		U32(512) << ltc_ltcs_ltss_cbc_param_cache_line_size_v(reg);
+
+	gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(),
+	g->ltc_count);
+	gk20a_writel(g, ltc_ltcs_misc_ltc_num_active_ltcs_r(),
+	g->ltc_count);
+
+	gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(),
+		     gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) |
+		     ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m());
+
+	/* Disable LTC interrupts */
+	reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
+	reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m();
+	reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m();
+	reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_m();
+	gk20a_writel(g, ltc_ltcs_ltss_intr_r(), reg);
+}
+
+void gm20b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice)
+{
+	u32 ltc_intr;
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+	ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() +
+			   ltc_stride * ltc +
+			   lts_stride * slice);
+	nvgpu_err(g, "ltc%d, slice %d: %08x",
+		  ltc, slice, ltc_intr);
+	gk20a_writel(g, ltc_ltc0_lts0_intr_r() +
+			   ltc_stride * ltc +
+			   lts_stride * slice,
+		     ltc_intr);
+}
+
+void gm20b_ltc_isr(struct gk20a *g, unsigned int ltc)
+{
+	unsigned int slice;
+
+	for (slice = 0U; slice < g->slices_per_ltc; slice++) {
+		gm20b_ltc_lts_isr(g, ltc, slice);
+	}
+}
+
+/*
+ * Performs a full flush of the L2 cache.
+ */
+void gm20b_flush_ltc(struct gk20a *g)
+{
+	struct nvgpu_timeout timeout;
+	unsigned int ltc;
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	bool is_clean_pending_set = false;
+	bool is_invalidate_pending_set = false;
+
+	/* Clean... */
+	nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_cmgmt1_r(),
+		ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f() |
+		ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f() |
+		ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f() |
+		ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f() |
+		ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f() |
+		ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f());
+
+	/* Wait on each LTC individually. */
+	for (ltc = 0; ltc < g->ltc_count; ltc++) {
+		u32 op_pending;
+
+		/*
+		 * Use 5ms - this should be sufficient time to flush the cache.
+		 * On tegra, rough EMC BW available for old tegra chips (newer
+		 * chips are strictly faster) can be estimated as follows:
+		 *
+		 * Lowest reasonable EMC clock speed will be around 102MHz on
+		 * t124 for display enabled boards and generally fixed to max
+		 * for non-display boards (since they are generally plugged in).
+		 *
+		 * Thus, the available BW is 64b * 2 * 102MHz = 1.3GB/s. Of that
+		 * BW the GPU will likely get about half (display and overhead/
+		 * utilization inefficiency eating the rest) so 650MB/s at
+		 * worst. Assuming at most 1MB of GPU L2 cache (less for most
+		 * chips) worst case is we take 1MB/650MB/s = 1.5ms.
+		 *
+		 * So 5ms timeout here should be more than sufficient.
+		 */
+		nvgpu_timeout_init(g, &timeout, 5, NVGPU_TIMER_CPU_TIMER);
+
+		do {
+			int cmgmt1 = ltc_ltc0_ltss_tstg_cmgmt1_r() +
+				     ltc * ltc_stride;
+			op_pending = gk20a_readl(g, cmgmt1);
+			is_clean_pending_set = (op_pending &
+				ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f()) != 0U;
+		} while (is_clean_pending_set &&
+			(nvgpu_timeout_expired_msg(&timeout,
+					"L2 flush timeout!") == 0));
+	}
+
+	/* And invalidate. */
+	nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_cmgmt0_r(),
+	     ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f() |
+	     ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f() |
+	     ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f() |
+	     ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f() |
+	     ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f());
+
+	/* Wait on each LTC individually. */
+	for (ltc = 0; ltc < g->ltc_count; ltc++) {
+		u32 op_pending;
+
+		/* Again, 5ms. */
+		nvgpu_timeout_init(g, &timeout, 5, NVGPU_TIMER_CPU_TIMER);
+
+		do {
+			int cmgmt0 = ltc_ltc0_ltss_tstg_cmgmt0_r() +
+				     ltc * ltc_stride;
+			op_pending = gk20a_readl(g, cmgmt0);
+			is_invalidate_pending_set = (op_pending &
+				ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f()) != 0U;
+		} while (is_invalidate_pending_set &&
+			(nvgpu_timeout_expired_msg(&timeout,
+					"L2 flush timeout!") == 0));
+	}
+}
+
+int gm20b_determine_L2_size_bytes(struct gk20a *g)
+{
+	u32 lts_per_ltc;
+	u32 ways;
+	u32 sets;
+	u32 bytes_per_line;
+	u32 active_ltcs;
+	u32 cache_size;
+
+	u32 tmp;
+	u32 active_sets_value;
+
+	tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_cfg1_r());
+	ways = hweight32(ltc_ltc0_lts0_tstg_cfg1_active_ways_v(tmp));
+
+	active_sets_value = ltc_ltc0_lts0_tstg_cfg1_active_sets_v(tmp);
+	if (active_sets_value == ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v()) {
+		sets = 64U;
+	} else if (active_sets_value ==
+		 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v()) {
+		sets = 32U;
+	} else if (active_sets_value ==
+		 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v()) {
+		sets = 16U;
+	} else {
+		nvgpu_err(g, "Unknown constant %u for active sets",
+		       (unsigned)active_sets_value);
+		sets = 0U;
+	}
+
+	active_ltcs = g->gr.num_fbps;
+
+	/* chip-specific values */
+	lts_per_ltc = 2U;
+	bytes_per_line = 128U;
+	cache_size = active_ltcs * lts_per_ltc * ways * sets * bytes_per_line;
+
+	return cache_size;
+}
+
+/*
+ * Sets the ZBC color for the passed index.
+ */
+void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
+					  u32 *color_l2,
+					  u32 index)
+{
+	u32 i;
+
+	nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+		     ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
+
+	for (i = 0;
+	     i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) {
+		nvgpu_writel_check(g,
+			ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i),
+			color_l2[i]);
+	}
+}
+
+/*
+ * Sets the ZBC depth for the passed index.
+ */
+void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g,
+					  u32 depth_val,
+					  u32 index)
+{
+	nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+		     ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
+
+	nvgpu_writel_check(g,
+			ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(),
+			depth_val);
+}
+
+void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled)
+{
+	u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
+	u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r());
+
+	if (enabled) {
+		/* bypass disabled (normal caching ops) */
+		reg &= ~reg_f;
+	} else {
+		/* bypass enabled (no caching) */
+		reg |= reg_f;
+	}
+
+	gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
+}
+
+/*
+ * LTC pri addressing
+ */
+bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr)
+{
+	return ((addr >= ltc_pltcg_base_v()) && (addr < ltc_pltcg_extent_v()));
+}
+
+bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
+{
+	u32 ltc_shared_base = ltc_ltcs_ltss_v();
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+	return (addr >= ltc_shared_base) &&
+		(addr < (ltc_shared_base + lts_stride));
+}
+
+bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr)
+{
+	u32 lts_shared_base = ltc_ltc0_ltss_v();
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+	u32 addr_mask = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE) - 1U;
+	u32 base_offset = lts_shared_base & addr_mask;
+	u32 end_offset = base_offset + lts_stride;
+
+	return (!gm20b_ltc_is_ltcs_ltss_addr(g, addr)) &&
+		((addr & addr_mask) >= base_offset) &&
+		((addr & addr_mask) < end_offset);
+}
+
+static void gm20b_ltc_update_ltc_lts_addr(struct gk20a *g, u32 addr, u32 ltc_num,
+					u32 *priv_addr_table,
+					u32 *priv_addr_table_index)
+{
+	u32 num_ltc_slices = g->ops.top.get_max_lts_per_ltc(g);
+	u32 index = *priv_addr_table_index;
+	u32 lts_num;
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+	for (lts_num = 0; lts_num < num_ltc_slices; lts_num++) {
+		priv_addr_table[index++] = ltc_ltc0_lts0_v() +
+						ltc_num * ltc_stride +
+						lts_num * lts_stride +
+						(addr & (lts_stride - 1U));
+	}
+
+	*priv_addr_table_index = index;
+}
+
+void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
+					u32 *priv_addr_table,
+					u32 *priv_addr_table_index)
+{
+	u32 num_ltc = g->ltc_count;
+	u32 i, start, ltc_num = 0;
+	u32 pltcg_base = ltc_pltcg_base_v();
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+
+	for (i = 0; i < num_ltc; i++) {
+		start = pltcg_base + i * ltc_stride;
+		if ((addr >= start) && (addr < (start + ltc_stride))) {
+			ltc_num = i;
+			break;
+		}
+	}
+	gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num, priv_addr_table,
+				priv_addr_table_index);
+}
+
+void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
+					u32 *priv_addr_table,
+					u32 *priv_addr_table_index)
+{
+	u32 num_ltc = g->ltc_count;
+	u32 ltc_num;
+
+	for (ltc_num = 0; ltc_num < num_ltc; ltc_num++) {
+		gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num,
+					priv_addr_table, priv_addr_table_index);
+	}
+}

drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h

@@ -0,0 +1,55 @@
+/*
+ * GM20B L2
+ *
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_LTC_GM20B
+#define NVGPU_LTC_GM20B
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct gr_gk20a;
+
+int gm20b_determine_L2_size_bytes(struct gk20a *g);
+void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
+					  u32 *color_l2,
+					  u32 index);
+void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g,
+					  u32 depth_val,
+					  u32 index);
+void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled);
+void gm20b_ltc_init_fs_state(struct gk20a *g);
+void gm20b_ltc_isr(struct gk20a *g, unsigned int ltc);
+void gm20b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice);
+void gm20b_flush_ltc(struct gk20a *g);
+bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr);
+bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr);
+bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr);
+void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
+					u32 *priv_addr_table,
+					u32 *priv_addr_table_index);
+void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
+					u32 *priv_addr_table,
+					u32 *priv_addr_table_index);
+
+#endif

drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.c

@@ -0,0 +1,157 @@
+/*
+ * GP10B L2
+ *
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <trace/events/gk20a.h>
+
+#include <nvgpu/ltc.h>
+#include <nvgpu/log.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/gk20a.h>
+
+#include <nvgpu/hw/gp10b/hw_ltc_gp10b.h>
+
+#include "ltc_gm20b.h"
+#include "ltc_gp10b.h"
+
+int gp10b_determine_L2_size_bytes(struct gk20a *g)
+{
+	u32 tmp;
+	int ret;
+
+	nvgpu_log_fn(g, " ");
+
+	tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r());
+
+	ret = g->ltc_count *
+		ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp) * 1024U *
+		ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp);
+
+	nvgpu_log(g, gpu_dbg_info, "L2 size: %d\n", ret);
+
+	nvgpu_log_fn(g, "done");
+
+	return ret;
+}
+
+void gp10b_ltc_lts_isr(struct gk20a *g,	unsigned int ltc, unsigned int slice)
+{
+	u32 offset;
+	u32 ltc_intr;
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+	offset = ltc_stride * ltc + lts_stride * slice;
+	ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset);
+
+	/* Detect and handle ECC errors */
+	if ((ltc_intr &
+	     ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) != 0U) {
+		u32 ecc_stats_reg_val;
+
+		nvgpu_err(g,
+			"Single bit error detected in GPU L2!");
+
+		ecc_stats_reg_val =
+			gk20a_readl(g,
+				ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
+		g->ecc.ltc.ecc_sec_count[ltc][slice].counter +=
+			ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val);
+		ecc_stats_reg_val &=
+			~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m());
+		nvgpu_writel_check(g,
+			ltc_ltc0_lts0_dstg_ecc_report_r() + offset,
+			ecc_stats_reg_val);
+		if (g->ops.mm.l2_flush(g, true) != 0) {
+			nvgpu_err(g, "l2_flush failed");
+		}
+	}
+	if ((ltc_intr &
+	     ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) != 0U) {
+		u32 ecc_stats_reg_val;
+
+		nvgpu_err(g,
+			"Double bit error detected in GPU L2!");
+
+		ecc_stats_reg_val =
+			gk20a_readl(g,
+				ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
+		g->ecc.ltc.ecc_ded_count[ltc][slice].counter +=
+			ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val);
+		ecc_stats_reg_val &=
+			~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m());
+		nvgpu_writel_check(g,
+			ltc_ltc0_lts0_dstg_ecc_report_r() + offset,
+			ecc_stats_reg_val);
+	}
+
+	nvgpu_err(g, "ltc%d, slice %d: %08x",
+		  ltc, slice, ltc_intr);
+	nvgpu_writel_check(g, ltc_ltc0_lts0_intr_r() +
+		ltc_stride * ltc + lts_stride * slice,
+		ltc_intr);
+}
+
+void gp10b_ltc_isr(struct gk20a *g, unsigned int ltc)
+{
+	unsigned int slice;
+
+	for (slice = 0U; slice < g->slices_per_ltc; slice++) {
+		gp10b_ltc_lts_isr(g, ltc, slice);
+	}
+}
+
+void gp10b_ltc_init_fs_state(struct gk20a *g)
+{
+	u32 ltc_intr;
+
+	gm20b_ltc_init_fs_state(g);
+
+	gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(),
+			ltc_ltca_g_axi_pctrl_user_sid_f(g->ltc_streamid));
+
+	/* Enable ECC interrupts */
+	ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
+	ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
+			ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f();
+	gk20a_writel(g, ltc_ltcs_ltss_intr_r(),
+			ltc_intr);
+}
+
+void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled)
+{
+	u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
+	u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r());
+
+	if (enabled) {
+		/* bypass disabled (normal caching ops) */
+		reg &= ~reg_f;
+	} else {
+		/* bypass enabled (no caching) */
+		reg |= reg_f;
+	}
+
+	nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
+}

drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef LTC_GP10B_H
+#define LTC_GP10B_H
+struct gk20a;
+struct gpu_ops;
+
+int gp10b_determine_L2_size_bytes(struct gk20a *g);
+void gp10b_ltc_init_fs_state(struct gk20a *g);
+void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled);
+void gp10b_ltc_isr(struct gk20a *g, unsigned int ltc);
+void gp10b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice);
+#endif

drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.c

@@ -0,0 +1,244 @@
+/*
+ * GV11B LTC
+ *
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/nvgpu_err.h>
+
+#include "ltc_gp10b.h"
+#include "ltc_gv11b.h"
+
+#include <nvgpu/hw/gv11b/hw_ltc_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
+
+#include <nvgpu/utils.h>
+
+/*
+ * Sets the ZBC stencil for the passed index.
+ */
+void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
+					  u32 stencil_depth,
+					  u32 index)
+{
+	nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+		     ltc_ltcs_ltss_dstg_zbc_index_address_f(index));
+
+	nvgpu_writel_check(g,
+			   ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
+			   stencil_depth);
+}
+
+void gv11b_ltc_init_fs_state(struct gk20a *g)
+{
+	u32 ltc_intr;
+	u32 reg;
+
+	nvgpu_log_info(g, "initialize gv11b l2");
+
+	g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r());
+	g->ltc_count = g->ops.priv_ring.enum_ltc(g);
+	nvgpu_log_info(g, "%u ltcs out of %u", g->ltc_count, g->max_ltc_count);
+
+	reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r());
+	g->slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(reg);;
+	g->cacheline_size =
+		U32(512) << ltc_ltcs_ltss_cbc_param_cache_line_size_v(reg);
+
+	/* Disable LTC interrupts */
+	reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
+	reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m();
+	reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m();
+	nvgpu_writel_check(g, ltc_ltcs_ltss_intr_r(), reg);
+
+	if (g->ops.ltc.intr_en_illegal_compstat != NULL) {
+		g->ops.ltc.intr_en_illegal_compstat(g,
+					g->ltc_intr_en_illegal_compstat);
+	}
+
+	/* Enable ECC interrupts */
+	ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
+	ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
+		ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f();
+	nvgpu_writel_check(g, ltc_ltcs_ltss_intr_r(),
+				ltc_intr);
+}
+
+void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable)
+{
+	u32 val;
+
+	/* disble/enble illegal_compstat interrupt */
+	val = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
+	if (enable) {
+		val = set_field(val,
+			ltc_ltcs_ltss_intr_en_illegal_compstat_m(),
+			ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f());
+	} else {
+		val = set_field(val,
+			ltc_ltcs_ltss_intr_en_illegal_compstat_m(),
+			ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f());
+        }
+	gk20a_writel(g, ltc_ltcs_ltss_intr_r(), val);
+}
+
+void gv11b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice)
+{
+	u32 offset;
+	u32 ltc_intr3;
+	u32 ecc_status, ecc_addr, dstg_ecc_addr, corrected_cnt, uncorrected_cnt;
+	u32 corrected_delta, uncorrected_delta;
+	u32 corrected_overflow, uncorrected_overflow;
+	u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+	u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+	offset = ltc_stride * ltc + lts_stride * slice;
+	ltc_intr3 = gk20a_readl(g, ltc_ltc0_lts0_intr3_r() +
+				offset);
+
+	/* Detect and handle ECC PARITY errors */
+	if ((ltc_intr3 &
+		(ltc_ltcs_ltss_intr3_ecc_uncorrected_m() |
+		 ltc_ltcs_ltss_intr3_ecc_corrected_m())) != 0U) {
+
+		ecc_status = gk20a_readl(g,
+			ltc_ltc0_lts0_l2_cache_ecc_status_r() +
+			offset);
+		ecc_addr = gk20a_readl(g,
+			ltc_ltc0_lts0_l2_cache_ecc_address_r() +
+			offset);
+		dstg_ecc_addr = gk20a_readl(g,
+			ltc_ltc0_lts0_dstg_ecc_address_r() +
+			offset);
+		corrected_cnt = gk20a_readl(g,
+			ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset);
+		uncorrected_cnt = gk20a_readl(g,
+			ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset);
+
+		corrected_delta =
+			ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(corrected_cnt);
+		uncorrected_delta =
+			ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(uncorrected_cnt);
+		corrected_overflow = ecc_status &
+			ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m();
+
+		uncorrected_overflow = ecc_status &
+			ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m();
+
+		/* clear the interrupt */
+		if ((corrected_delta > 0U) || (corrected_overflow != 0U)) {
+			nvgpu_writel_check(g,
+				ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0);
+		}
+		if ((uncorrected_delta > 0U) || (uncorrected_overflow !=0U)) {
+			nvgpu_writel_check(g,
+				ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0);
+		}
+
+		nvgpu_writel_check(g,
+			ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset,
+			ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f());
+
+		/* update counters per slice */
+		if (corrected_overflow != 0U) {
+			corrected_delta += BIT32(ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s());
+		}
+		if (uncorrected_overflow != 0U) {
+			uncorrected_delta += BIT32(ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s());
+		}
+
+		g->ecc.ltc.ecc_sec_count[ltc][slice].counter += corrected_delta;
+		g->ecc.ltc.ecc_ded_count[ltc][slice].counter += uncorrected_delta;
+		nvgpu_log(g, gpu_dbg_intr,
+			"ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3);
+
+		if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()) != 0U) {
+			nvgpu_ltc_report_ecc_error(g, ltc, slice,
+					GPU_LTC_CACHE_RSTG_ECC_CORRECTED, ecc_addr,
+					g->ecc.ltc.ecc_sec_count[ltc][slice].counter);
+			nvgpu_log(g, gpu_dbg_intr, "rstg ecc error corrected");
+		}
+		if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()) != 0U) {
+			nvgpu_ltc_report_ecc_error(g, ltc, slice,
+					GPU_LTC_CACHE_RSTG_ECC_UNCORRECTED, ecc_addr,
+					g->ecc.ltc.ecc_ded_count[ltc][slice].counter);
+			nvgpu_log(g, gpu_dbg_intr, "rstg ecc error uncorrected");
+		}
+		if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m()) != 0U) {
+			nvgpu_ltc_report_ecc_error(g, ltc, slice,
+					GPU_LTC_CACHE_TSTG_ECC_CORRECTED, ecc_addr,
+					g->ecc.ltc.ecc_sec_count[ltc][slice].counter);
+			nvgpu_log(g, gpu_dbg_intr, "tstg ecc error corrected");
+		}
+		if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m()) != 0U) {
+			nvgpu_ltc_report_ecc_error(g, ltc, slice,
+					GPU_LTC_CACHE_TSTG_ECC_UNCORRECTED, ecc_addr,
+					g->ecc.ltc.ecc_ded_count[ltc][slice].counter);
+			nvgpu_log(g, gpu_dbg_intr, "tstg ecc error uncorrected");
+		}
+		if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m()) != 0U) {
+			if ((dstg_ecc_addr & ltc_ltc0_lts0_dstg_ecc_address_info_ram_m()) == 0U) {
+				nvgpu_ltc_report_ecc_error(g, ltc, slice,
+						GPU_LTC_CACHE_DSTG_ECC_CORRECTED, ecc_addr,
+						g->ecc.ltc.ecc_sec_count[ltc][slice].counter);
+			} else {
+				nvgpu_ltc_report_ecc_error(g, ltc, slice,
+						GPU_LTC_CACHE_DSTG_BE_ECC_CORRECTED, ecc_addr,
+						g->ecc.ltc.ecc_sec_count[ltc][slice].counter);
+			}
+			nvgpu_log(g, gpu_dbg_intr, "dstg ecc error corrected");
+		}
+		if ((ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m()) != 0U) {
+			if ((dstg_ecc_addr & ltc_ltc0_lts0_dstg_ecc_address_info_ram_m()) == 0U) {
+				nvgpu_ltc_report_ecc_error(g, ltc, slice,
+						GPU_LTC_CACHE_DSTG_ECC_UNCORRECTED, ecc_addr,
+						g->ecc.ltc.ecc_ded_count[ltc][slice].counter);
+			} else {
+				nvgpu_ltc_report_ecc_error(g, ltc, slice,
+						GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED, ecc_addr,
+						g->ecc.ltc.ecc_ded_count[ltc][slice].counter);
+			}
+			nvgpu_log(g, gpu_dbg_intr, "dstg ecc error uncorrected");
+		}
+
+		if ((corrected_overflow != 0U) || (uncorrected_overflow != 0U)) {
+			nvgpu_info(g, "ecc counter overflow!");
+		}
+
+		nvgpu_log(g, gpu_dbg_intr,
+			"ecc error address: 0x%x", ecc_addr);
+	}
+
+	gp10b_ltc_lts_isr(g, ltc, slice);
+}
+
+void gv11b_ltc_isr(struct gk20a *g, unsigned int ltc)
+{
+	unsigned int slice;
+
+	for (slice = 0U; slice < g->slices_per_ltc; slice++) {
+		gv11b_ltc_lts_isr(g, ltc, slice);
+	}
+}

drivers/gpu/nvgpu/hal/ltc/ltc_gv11b.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef LTC_GV11B_H
+#define LTC_GV11B_H
+struct gk20a;
+
+void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
+					  u32 stencil_depth,
+					  u32 index);
+void gv11b_ltc_init_fs_state(struct gk20a *g);
+void gv11b_ltc_intr_en_illegal_compstat(struct gk20a *g, bool enable);
+void gv11b_ltc_isr(struct gk20a *g, unsigned int ltc);
+void gv11b_ltc_lts_isr(struct gk20a *g, unsigned int ltc, unsigned int slice);
+
+#endif

drivers/gpu/nvgpu/hal/ltc/ltc_tu104.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/ltc.h>
+#include <nvgpu/comptags.h>
+#include <nvgpu/io.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/gk20a.h>
+
+#include <trace/events/gk20a.h>
+
+#include "ltc_tu104.h"
+
+#include "ltc_gv11b.h"
+
+#include <nvgpu/hw/tu104/hw_ltc_tu104.h>
+
+void ltc_tu104_init_fs_state(struct gk20a *g)
+{
+	u32 reg;
+
+	gv11b_ltc_init_fs_state(g);
+
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_cbc_param2_r());
+	g->slices_per_ltc =
+		ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(reg);
+	g->cacheline_size =
+		U32(512) << ltc_ltcs_ltss_cbc_param2_cache_line_size_v(reg);
+
+	/* disable PLC compression */
+	reg = nvgpu_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r());
+	reg = set_field(reg,
+		ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_m(),
+		ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_disabled_f());
+	reg = set_field(reg,
+		ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_m(),
+		ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f());
+	nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r(), reg);
+}

drivers/gpu/nvgpu/hal/ltc/ltc_tu104.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef LTC_TU104_H
+#define LTC_TU104_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void ltc_tu104_init_fs_state(struct gk20a *g);
+
+#endif