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gpu: nvgpu: fix various MISRA 10.1 bool violations

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This patch corrects a handful of MISRA 10.1 violations involving
illegal arithmetic operations (e.g. bitwise OR) on boolean values:

 * fix to status handling in regops validation code
 * fix to debugger event handling in gr code
 * fix to entries_left tracking in runlist construct code
 * fix to verbose channel dumping and reset tracking in fifo code

JIRA NVGPU-650

Change-Id: I3c3d9123b5a0e08fc936d0e63d51de99fc310ade
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810957
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Scott Long
2018-08-31 15:43:24 -07:00
committed by mobile promotions
parent cf394f82d4
commit a18f364fd2
3 changed files with 22 additions and 15 deletions
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11
drivers/gpu/nvgpu/gk20a/regops_gk20a.c
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@@ -404,7 +404,6 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
u32 op_count)
{
u32 i;
int err;
bool ok = true;
struct gk20a *g = dbg_s->g;
@@ -412,8 +411,9 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
* a separate error code if needed */
for (i = 0; i < op_count; i++) {
err = validate_reg_op_info(dbg_s, &ops[i]);
ok &= !err;
if (validate_reg_op_info(dbg_s, &ops[i]) != 0) {
ok = false;
}
if (reg_op_is_gr_ctx(ops[i].type)) {
if (reg_op_is_read(ops[i].op))
@@ -424,8 +424,9 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
/* if "allow_all" flag enabled, dont validate offset */
if (!g->allow_all) {
err = validate_reg_op_offset(dbg_s, &ops[i]);
ok &= !err;
if (validate_reg_op_offset(dbg_s, &ops[i]) != 0) {
ok = false;
}
}
}