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gpu: nvgpu: Enable CE in GR reset

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Enable GRCE when enabling GR. Also use the reset mask read from
device info instead of using the hard coded value.

Change-Id: I4812c32d09ea8b5e07abd1b2c6f1efdbe00cb36e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1149359
This commit is contained in:
Terje Bergstrom
2016-05-17 15:17:23 -07:00
parent 9e908d2a8d
commit a21dcf0bc6
2 changed files with 5 additions and 3 deletions
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3
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -379,8 +379,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
gk20a_dbg_fn("");
/* enable pmc pfifo */
gk20a_reset(g, mc_enable_pfifo_enabled_f()
| mc_enable_ce2_enabled_f());
gk20a_reset(g, mc_enable_pfifo_enabled_f());
if (g->ops.clock_gating.slcg_ce2_load_gating_prod)
g->ops.clock_gating.slcg_ce2_load_gating_prod(g,

5
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -4550,6 +4550,8 @@ static int gk20a_init_gr_prepare(struct gk20a *g)
{
u32 gpfifo_ctrl, pmc_en;
u32 err = 0;
struct fifo_engine_info_gk20a *ce_info =
g->fifo.engine_info + ENGINE_CE2_GK20A;
/* disable fifo access */
pmc_en = gk20a_readl(g, mc_enable_r());
@@ -4562,7 +4564,8 @@ static int gk20a_init_gr_prepare(struct gk20a *g)
/* reset gr engine */
gk20a_reset(g, mc_enable_pgraph_enabled_f()
| mc_enable_blg_enabled_f()
| mc_enable_perfmon_enabled_f());
| mc_enable_perfmon_enabled_f()
| ce_info->reset_mask);
gr_gk20a_load_gating_prod(g);
/* Disable elcg until it gets enabled later in the init*/