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gpu: nvgpu: fix PRE31-C violations in wpr/vpr dump

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nvgpu_err() macro with a nvgpu_readl() call results in
a volatile access. This violates PRE31-C rule - "Using an
unsafe function-like macro with side effect in argument
nvgpu_readl()" due to side effect of a volatile access.

Fix this by moving nvgpu_readl() calls before nvgpu_err().

The messages log VPR and WPR address info. There are no
known attacks using this info. So it shall be safe to
reveal address info.

JIRA NVGPU-3908

Change-Id: I487a0c0858fe9a36cc81852cedd7757aab277c6a
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2178416
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Nitin Kumbhar
2019-08-19 16:43:20 +05:30
committed by mobile promotions
parent bcc21dbd0b
commit a232eb8d20
1 changed files with 22 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
drivers/gpu/nvgpu/hal/fb/fb_gm20b_fusa.c
View File

@@ -212,35 +212,47 @@ u32 gm20b_fb_mmu_debug_rd(struct gk20a *g)
void gm20b_fb_dump_vpr_info(struct gk20a *g)
{
u32 val;
u32 addr_lo, addr_hi, cya_lo, cya_hi;
/* print vpr info */
val = gk20a_readl(g, fb_mmu_vpr_info_r());
val &= ~0x3U;
val |= fb_mmu_vpr_info_index_addr_lo_v();
gk20a_writel(g, fb_mmu_vpr_info_r(), val);
addr_lo = gk20a_readl(g, fb_mmu_vpr_info_r());
addr_hi = gk20a_readl(g, fb_mmu_vpr_info_r());
cya_lo = gk20a_readl(g, fb_mmu_vpr_info_r());
cya_hi = gk20a_readl(g, fb_mmu_vpr_info_r());
nvgpu_err(g, "VPR: %08x %08x %08x %08x",
gk20a_readl(g, fb_mmu_vpr_info_r()),
gk20a_readl(g, fb_mmu_vpr_info_r()),
gk20a_readl(g, fb_mmu_vpr_info_r()),
gk20a_readl(g, fb_mmu_vpr_info_r()));
addr_lo, addr_hi, cya_lo, cya_hi);
}
void gm20b_fb_dump_wpr_info(struct gk20a *g)
{
u32 val;
u32 allow_read, allow_write;
u32 wpr1_addr_lo, wpr1_addr_hi;
u32 wpr2_addr_lo, wpr2_addr_hi;
/* print wpr info */
val = gk20a_readl(g, fb_mmu_wpr_info_r());
val &= ~0xfU;
val |= (fb_mmu_wpr_info_index_allow_read_v());
gk20a_writel(g, fb_mmu_wpr_info_r(), val);
allow_read = gk20a_readl(g, fb_mmu_wpr_info_r());
allow_write = gk20a_readl(g, fb_mmu_wpr_info_r());
wpr1_addr_lo = gk20a_readl(g, fb_mmu_wpr_info_r());
wpr1_addr_hi = gk20a_readl(g, fb_mmu_wpr_info_r());
wpr2_addr_lo = gk20a_readl(g, fb_mmu_wpr_info_r());
wpr2_addr_hi = gk20a_readl(g, fb_mmu_wpr_info_r());
nvgpu_err(g, "WPR: %08x %08x %08x %08x %08x %08x",
gk20a_readl(g, fb_mmu_wpr_info_r()),
gk20a_readl(g, fb_mmu_wpr_info_r()),
gk20a_readl(g, fb_mmu_wpr_info_r()),
gk20a_readl(g, fb_mmu_wpr_info_r()),
gk20a_readl(g, fb_mmu_wpr_info_r()),
gk20a_readl(g, fb_mmu_wpr_info_r()));
allow_read, allow_write,
wpr1_addr_lo, wpr1_addr_hi,
wpr2_addr_lo, wpr2_addr_hi);
}
static int gm20b_fb_vpr_info_fetch_wait(struct gk20a *g,