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gpu: nvgpu: add debugger flag for fb units

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Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.hal.fb unit

Jira NVGPU-3506

Change-Id: If459e623e73ce716088d9cb92c31864c26fe0d3d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132260
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-06-06 17:15:10 +05:30
committed by mobile promotions
parent 1112af9f8c
commit a3d30adab2
12 changed files with 24 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/init/nvgpu_init.c
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@@ -474,8 +474,10 @@ int gk20a_finalize_poweron(struct gk20a *g)
g->ops.chip_init_gpu_characteristics(g); g->ops.chip_init_gpu_characteristics(g);
#ifdef CONFIG_NVGPU_DEBUGGER
/* Restore the debug setting */ /* Restore the debug setting */
g->ops.fb.set_debug_mode(g, g->mmu_debug_ctrl); g->ops.fb.set_debug_mode(g, g->mmu_debug_ctrl);
#endif
#ifdef CONFIG_NVGPU_CE #ifdef CONFIG_NVGPU_CE
err = nvgpu_ce_init_support(g); err = nvgpu_ce_init_support(g);

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
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@@ -394,8 +394,10 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.dump_vpr_info = NULL, .dump_vpr_info = NULL,
.dump_wpr_info = NULL, .dump_wpr_info = NULL,
.read_wpr_info = NULL, .read_wpr_info = NULL,
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = NULL, .is_debug_mode_enabled = NULL,
.set_debug_mode = vgpu_mm_mmu_set_debug_mode, .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
#endif
.tlb_invalidate = vgpu_mm_tlb_invalidate, .tlb_invalidate = vgpu_mm_tlb_invalidate,
}, },
.cg = { .cg = {

2
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
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@@ -460,8 +460,10 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.dump_vpr_info = NULL, .dump_vpr_info = NULL,
.dump_wpr_info = NULL, .dump_wpr_info = NULL,
.read_wpr_info = NULL, .read_wpr_info = NULL,
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = NULL, .is_debug_mode_enabled = NULL,
.set_debug_mode = vgpu_mm_mmu_set_debug_mode, .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
#endif
.tlb_invalidate = vgpu_mm_tlb_invalidate, .tlb_invalidate = vgpu_mm_tlb_invalidate,
.write_mmu_fault_buffer_lo_hi = .write_mmu_fault_buffer_lo_hi =
gv11b_fb_write_mmu_fault_buffer_lo_hi, gv11b_fb_write_mmu_fault_buffer_lo_hi,

2
drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c
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@@ -214,6 +214,7 @@ int vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
return 0; return 0;
} }
#ifdef CONFIG_NVGPU_DEBUGGER
void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
{ {
struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_cmd_msg msg;
@@ -228,6 +229,7 @@ void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
WARN_ON(err || msg.ret); WARN_ON(err || msg.ret);
} }
#endif
static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc,
u64 addr, u64 size, size_t *oob_size) u64 addr, u64 size, size_t *oob_size)

2
drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.h
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@@ -46,7 +46,9 @@ int vgpu_mm_fb_flush(struct gk20a *g);
void vgpu_mm_l2_invalidate(struct gk20a *g); void vgpu_mm_l2_invalidate(struct gk20a *g);
int vgpu_mm_l2_flush(struct gk20a *g, bool invalidate); int vgpu_mm_l2_flush(struct gk20a *g, bool invalidate);
int vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb); int vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
#ifdef CONFIG_NVGPU_DEBUGGER
void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable); void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable);
#endif
u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
u64 map_offset, u64 map_offset,
struct nvgpu_sgt *sgt, struct nvgpu_sgt *sgt,

4
drivers/gpu/nvgpu/hal/fb/fb_gm20b.c
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@@ -326,6 +326,7 @@ void gm20b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size)
*wpr_size = (wpr_end - wpr_start); *wpr_size = (wpr_end - wpr_start);
} }
#ifdef CONFIG_NVGPU_DEBUGGER
bool gm20b_fb_debug_mode_enabled(struct gk20a *g) bool gm20b_fb_debug_mode_enabled(struct gk20a *g)
{ {
u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r()); u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r());
@@ -350,7 +351,6 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
#ifdef CONFIG_NVGPU_DEBUGGER
g->ops.gr.set_debug_mode(g, enable); g->ops.gr.set_debug_mode(g, enable);
#endif
} }
#endif

2
drivers/gpu/nvgpu/hal/fb/fb_gm20b.h
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@@ -48,7 +48,9 @@ void gm20b_fb_dump_vpr_info(struct gk20a *g);
void gm20b_fb_dump_wpr_info(struct gk20a *g); void gm20b_fb_dump_wpr_info(struct gk20a *g);
void gm20b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size); void gm20b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size);
int gm20b_fb_vpr_info_fetch(struct gk20a *g); int gm20b_fb_vpr_info_fetch(struct gk20a *g);
#ifdef CONFIG_NVGPU_DEBUGGER
bool gm20b_fb_debug_mode_enabled(struct gk20a *g); bool gm20b_fb_debug_mode_enabled(struct gk20a *g);
void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable); void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable);
#endif
#endif #endif

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
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@@ -537,8 +537,10 @@ static const struct gpu_ops gm20b_ops = {
.dump_vpr_info = gm20b_fb_dump_vpr_info, .dump_vpr_info = gm20b_fb_dump_vpr_info,
.dump_wpr_info = gm20b_fb_dump_wpr_info, .dump_wpr_info = gm20b_fb_dump_wpr_info,
.read_wpr_info = gm20b_fb_read_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info,
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode, .set_debug_mode = gm20b_fb_set_debug_mode,
#endif
.tlb_invalidate = gm20b_fb_tlb_invalidate, .tlb_invalidate = gm20b_fb_tlb_invalidate,
.mem_unlock = NULL, .mem_unlock = NULL,
}, },

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
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@@ -606,8 +606,10 @@ static const struct gpu_ops gp10b_ops = {
.dump_vpr_info = gm20b_fb_dump_vpr_info, .dump_vpr_info = gm20b_fb_dump_vpr_info,
.dump_wpr_info = gm20b_fb_dump_wpr_info, .dump_wpr_info = gm20b_fb_dump_wpr_info,
.read_wpr_info = gm20b_fb_read_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info,
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode, .set_debug_mode = gm20b_fb_set_debug_mode,
#endif
.tlb_invalidate = gm20b_fb_tlb_invalidate, .tlb_invalidate = gm20b_fb_tlb_invalidate,
.mem_unlock = NULL, .mem_unlock = NULL,
}, },

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
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@@ -713,8 +713,10 @@ static const struct gpu_ops gv11b_ops = {
.dump_vpr_info = gm20b_fb_dump_vpr_info, .dump_vpr_info = gm20b_fb_dump_vpr_info,
.dump_wpr_info = gm20b_fb_dump_wpr_info, .dump_wpr_info = gm20b_fb_dump_wpr_info,
.read_wpr_info = gm20b_fb_read_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info,
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode, .set_debug_mode = gm20b_fb_set_debug_mode,
#endif
.tlb_invalidate = gm20b_fb_tlb_invalidate, .tlb_invalidate = gm20b_fb_tlb_invalidate,
.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault, .handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,
.mem_unlock = NULL, .mem_unlock = NULL,

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
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@@ -749,8 +749,10 @@ static const struct gpu_ops tu104_ops = {
.dump_vpr_info = NULL, .dump_vpr_info = NULL,
.dump_wpr_info = gm20b_fb_dump_wpr_info, .dump_wpr_info = gm20b_fb_dump_wpr_info,
.read_wpr_info = gm20b_fb_read_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info,
#ifdef CONFIG_NVGPU_DEBUGGER
.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
.set_debug_mode = gm20b_fb_set_debug_mode, .set_debug_mode = gm20b_fb_set_debug_mode,
#endif
.tlb_invalidate = fb_tu104_tlb_invalidate, .tlb_invalidate = fb_tu104_tlb_invalidate,
.handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault, .handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault,
.mem_unlock = gv100_fb_memory_unlock, .mem_unlock = gv100_fb_memory_unlock,

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
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@@ -921,8 +921,10 @@ struct gpu_ops {
void (*dump_wpr_info)(struct gk20a *g); void (*dump_wpr_info)(struct gk20a *g);
int (*vpr_info_fetch)(struct gk20a *g); int (*vpr_info_fetch)(struct gk20a *g);
void (*read_wpr_info)(struct gk20a *g, u64 *wpr_base, u64 *wpr_size); void (*read_wpr_info)(struct gk20a *g, u64 *wpr_base, u64 *wpr_size);
#ifdef CONFIG_NVGPU_DEBUGGER
bool (*is_debug_mode_enabled)(struct gk20a *g); bool (*is_debug_mode_enabled)(struct gk20a *g);
void (*set_debug_mode)(struct gk20a *g, bool enable); void (*set_debug_mode)(struct gk20a *g, bool enable);
#endif
int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb); int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb);
void (*handle_replayable_fault)(struct gk20a *g); void (*handle_replayable_fault)(struct gk20a *g);
int (*mem_unlock)(struct gk20a *g); int (*mem_unlock)(struct gk20a *g);