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gpu: nvgpu: power_features: address code inspection gaps

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Address following code inspection gaps:
1. Fix the header guards for *gating_reglist.h files.
2. Remove ctxsw_firmware slcg/blcg mention from doxygen
   comments as that hal is removed.
3. Add therm slcg function and description to doxygen.
4. Add defgroups for including enums/macros in swud.

JIRA NVGPU-4797

Change-Id: I26f2e50b556bcac1486175143ab070f0c3c56c36
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288030
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2020-01-31 11:18:25 +05:30
committed by Alex Waterman
parent 14384edb68
commit a3ef9cf7df
6 changed files with 70 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/hal/power_features/cg/gating_reglist.h
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@@ -1,6 +1,6 @@
/*
*
* Copyright (c) 2018, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA Corporation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
*
*/
#ifndef GATING_REGLIST_H
#define GATING_REGLIST_H
#ifndef NVGPU_CG_GATING_REGLIST_H
#define NVGPU_CG_GATING_REGLIST_H
#include <nvgpu/types.h>
@@ -33,4 +33,4 @@ struct gating_desc {
u32 disable;
};
#endif /* GATING_REGLIST_H */
#endif /* NVGPU_CG_GATING_REGLIST_H */

8
drivers/gpu/nvgpu/hal/power_features/cg/gm20b_gating_reglist.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
* This file is autogenerated. Do not edit.
*/
#ifndef GM20B_GATING_REGLIST_H
#define GM20B_GATING_REGLIST_H
#ifndef NVGPU_CG_GM20B_GATING_REGLIST_H
#define NVGPU_CG_GM20B_GATING_REGLIST_H
#include <nvgpu/types.h>
@@ -125,4 +125,4 @@ void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g,
u32 gm20b_blcg_xbar_gating_prod_size(void);
const struct gating_desc *gm20b_blcg_xbar_get_gating_prod(void);
#endif /* GM20B_GATING_REGLIST_H */
#endif /* NVGPU_CG_GM20B_GATING_REGLIST_H */

8
drivers/gpu/nvgpu/hal/power_features/cg/gp10b_gating_reglist.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
* This file is autogenerated. Do not edit.
*/
#ifndef GP10B_GATING_REGLIST_H
#define GP10B_GATING_REGLIST_H
#ifndef NVGPU_CG_GP10B_GATING_REGLIST_H
#define NVGPU_CG_GP10B_GATING_REGLIST_H
#include <nvgpu/types.h>
@@ -130,4 +130,4 @@ void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
u32 gp10b_blcg_xbar_gating_prod_size(void);
const struct gating_desc *gp10b_blcg_xbar_get_gating_prod(void);
#endif /* GP10B_GATING_REGLIST_H */
#endif /* NVGPU_CG_GP10B_GATING_REGLIST_H */

8
drivers/gpu/nvgpu/hal/power_features/cg/gv11b_gating_reglist.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
* This file is autogenerated. Do not edit.
*/
#ifndef GV11B_GATING_REGLIST_H
#define GV11B_GATING_REGLIST_H
#ifndef NVGPU_CG_GV11B_GATING_REGLIST_H
#define NVGPU_CG_GV11B_GATING_REGLIST_H
#include <nvgpu/types.h>
@@ -140,4 +140,4 @@ void gv11b_blcg_hshub_load_gating_prod(struct gk20a *g,
u32 gv11b_blcg_hshub_gating_prod_size(void);
const struct gating_desc *gv11b_blcg_hshub_get_gating_prod(void);
#endif /* GV11B_GATING_REGLIST_H */
#endif /* NVGPU_CG_GV11B_GATING_REGLIST_H */

8
drivers/gpu/nvgpu/hal/power_features/cg/tu104_gating_reglist.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
* This file is autogenerated. Do not edit.
*/
#ifndef TU104_GATING_REGLIST_H
#define TU104_GATING_REGLIST_H
#ifndef NVGPU_CG_TU104_GATING_REGLIST_H
#define NVGPU_CG_TU104_GATING_REGLIST_H
#include <nvgpu/types.h>
@@ -140,4 +140,4 @@ void tu104_blcg_hshub_load_gating_prod(struct gk20a *g,
u32 tu104_blcg_hshub_gating_prod_size(void);
const struct gating_desc *tu104_blcg_hshub_get_gating_prod(void);
#endif /* TU104_GATING_REGLIST_H */
#endif /* NVGPU_CG_TU104_GATING_REGLIST_H */

70
drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -52,7 +52,7 @@
* + bus - GR init.
* + Chiplet - GR init.
* + GR - GR init.
* + CTXSW firmware - GR init.
* + THERM - THERM init.
* + PERF - GR init.
* + XBAR - GR init.
* + HSHUB - GR init.
@@ -65,7 +65,6 @@
* + CE - CE init.
* + GR - Golden context creation, GR init.
* + bus - GR init.
* + CTXSW firmware - GR init.
* + XBAR - GR init.
* + HSHUB - GR init.
*
@@ -107,6 +106,7 @@
* + nvgpu_cg_slcg_priring_load_enable()
* + nvgpu_cg_slcg_fifo_load_enable()
* + nvgpu_cg_slcg_pmu_load_enable()
* + nvgpu_cg_slcg_therm_load_enable()
* + nvgpu_cg_slcg_ce2_load_enable()
*
*/
@@ -115,34 +115,67 @@
#include <nvgpu/bitops.h>
/**
* Parameters for init_elcg_mode/init_blcg_mode.
* @defgroup NVGPU_ELCG_MODE_DEFINES
*
* Parameters for init_elcg_mode.
*/
/** Engine level clk always running, i.e. disable elcg. */
/**
* @ingroup NVGPU_ELCG_MODE_DEFINES
* Engine level clk always running, i.e. disable elcg.
*/
#define ELCG_RUN BIT32(0U)
/** Engine level clk is stopped. */
/**
* @ingroup NVGPU_ELCG_MODE_DEFINES
* Engine level clk is stopped.
*/
#define ELCG_STOP BIT32(1U)
/** Engine level clk will run when non-idle, i.e. standard elcg mode. */
/**
* @ingroup NVGPU_ELCG_MODE_DEFINES
* Engine level clk will run when non-idle, i.e. standard elcg mode.
*/
#define ELCG_AUTO BIT32(2U)
/** Block level clk always running, i.e. disable blcg. */
/**
* @defgroup NVGPU_BLCG_MODE_DEFINES
*
* Parameters for init_blcg_mode.
*/
/**
* @ingroup NVGPU_BLCG_MODE_DEFINES
* Block level clk always running, i.e. disable blcg.
*/
#define BLCG_RUN BIT32(0U)
/** Block level clk will run when non-idle, i.e. standard blcg mode. */
/**
* @ingroup NVGPU_BLCG_MODE_DEFINES
* Block level clk will run when non-idle, i.e. standard blcg mode.
*/
#define BLCG_AUTO BIT32(1U)
/**
* @defgroup NVGPU_CG_MODE_DEFINES
*
* Mode to be configured in engine gate ctrl registers.
*/
/** Engine Level Clock Gating (ELCG) Mode. */
/**
* @ingroup NVGPU_CG_MODE_DEFINES
* Engine Level Clock Gating (ELCG) Mode.
*/
#define ELCG_MODE BIT32(0U)
/** Block Level Clock Gating (BLCG) Mode. */
/**
* @ingroup NVGPU_CG_MODE_DEFINES
* Block Level Clock Gating (BLCG) Mode.
*/
#define BLCG_MODE BIT32(1U)
/** Invalid Mode. */
/**
* @ingroup NVGPU_CG_MODE_DEFINES
* Invalid Mode.
*/
#define INVALID_MODE BIT32(2U)
struct gk20a;
struct nvgpu_fifo;
/**
* @brief Load register configuration for ELCG and BLCG for GR related units.
@@ -150,18 +183,15 @@ struct nvgpu_fifo;
* @param g [in] The GPU driver struct.
*
* This function programs ELCG configuration for bus, chiplet, gr, perf,
* ctxsw_firmware, xbar, hshub units and BLCG for bus, gr, ctxsw_firmware,
* xbar and hshub. This is called in #nvgpu_gr_enable_hw after resetting GR
* engine.
* xbar, hshub units and BLCG for bus, gr, xbar and hshub. This is
* called in #nvgpu_gr_enable_hw after resetting GR engine.
*
* Steps:
* - Acquire the mutex #cg_pg_lock.
* - Check if #slcg_enabled is set, else skip SLCG programming.
* - Load SLCG prod settings for bus, chiplet, gr, ctxsw_firmware, perf,
* xbar, hshub.
* - Load SLCG prod settings for bus, chiplet, gr, perf, xbar, hshub.
* - Check if #blcg_enabled is set, else skip BLCG programming.
* - Load BLCG prod settings for bus, gr, ctxsw_firmware, xbar, hshub.
* - Load GR pg prod settings.
* - Load BLCG prod settings for bus, gr, xbar, hshub.
* - Release the mutex #cg_pg_lock.
*/
void nvgpu_cg_init_gr_load_gating_prod(struct gk20a *g);