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gpu: nvgpu: gp10b: fix stall interrupt enablement

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Currently priv, pbus and ltc interrupts are enabled as non-stall but
being handled in stall isr. Fix is to configure them as stall interrupt.

Change-Id: I78a0ad3eb4207dcd70da63098234ed6139f0664a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1320031
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2017-03-13 12:03:25 -07:00
committed by mobile promotions
parent 93ba29c5b5
commit a4deb1079e
1 changed files with 8 additions and 8 deletions
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16
drivers/gpu/nvgpu/gp10b/mc_gp10b.c
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@@ -29,20 +29,20 @@ void mc_gp10b_intr_enable(struct gk20a *g)
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
0xffffffff);
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
mc_intr_pfifo_pending_f()
| mc_intr_replayable_fault_pending_f()
| eng_intr_mask;
mc_intr_pfifo_pending_f() |
mc_intr_priv_ring_pending_f() |
mc_intr_pbus_pending_f() |
mc_intr_ltc_pending_f() |
mc_intr_replayable_fault_pending_f() |
eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
0xffffffff);
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
mc_intr_pfifo_pending_f()
| mc_intr_priv_ring_pending_f()
| mc_intr_ltc_pending_f()
| mc_intr_pbus_pending_f()
| eng_intr_mask;
mc_intr_pfifo_pending_f() |
eng_intr_mask;
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
}