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gpu: nvgpu: add info prints for sw_ctx_load and sw_non_ctx_load

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This will help debug issues where registers are incorrectly updated
by ctxsw ucode or are overwritten after nvgpu init sequence sets
the value.

Bug 3029888

Change-Id: I510763a767145500715fb260799b0dd98e59778f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2365212
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This commit is contained in:
Seema Khowala
2020-06-22 14:35:27 -07:00
committed by Alex Waterman
parent 7fea56cf97
commit a5ecf0da7c
2 changed files with 4 additions and 0 deletions
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2
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -573,6 +573,7 @@ static int gr_init_reset_enable_hw(struct gk20a *g)
enable_gr_interrupts(g); enable_gr_interrupts(g);
/* load non_ctx init */ /* load non_ctx init */
nvgpu_log_info(g, "begin: netlist: sw_non_ctx_load: register writes");
for (i = 0; i < sw_non_ctx_load->count; i++) { for (i = 0; i < sw_non_ctx_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_load->l[i].addr, nvgpu_writel(g, sw_non_ctx_load->l[i].addr,
sw_non_ctx_load->l[i].value); sw_non_ctx_load->l[i].value);
@@ -582,6 +583,7 @@ static int gr_init_reset_enable_hw(struct gk20a *g)
nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(g); nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(g);
nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(g); nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(g);
#endif #endif
nvgpu_log_info(g, "end: netlist: sw_non_ctx_load: register writes");
err = g->ops.gr.falcon.wait_mem_scrubbing(g); err = g->ops.gr.falcon.wait_mem_scrubbing(g);
if (err != 0) { if (err != 0) {

2
drivers/gpu/nvgpu/common/gr/obj_ctx.c
View File

@@ -467,10 +467,12 @@ static int nvgpu_gr_obj_ctx_init_hw_state(struct gk20a *g,
err = g->ops.gr.init.wait_idle(g); err = g->ops.gr.init.wait_idle(g);
/* load ctx init */ /* load ctx init */
nvgpu_log_info(g, "begin: netlist: sw_ctx_load: register writes");
for (i = 0U; i < sw_ctx_load->count; i++) { for (i = 0U; i < sw_ctx_load->count; i++) {
nvgpu_writel(g, sw_ctx_load->l[i].addr, nvgpu_writel(g, sw_ctx_load->l[i].addr,
sw_ctx_load->l[i].value); sw_ctx_load->l[i].value);
} }
nvgpu_log_info(g, "end: netlist: sw_ctx_load: register writes");
#ifdef CONFIG_NVGPU_GRAPHICS #ifdef CONFIG_NVGPU_GRAPHICS
if (g->ops.gr.init.preemption_state != NULL) { if (g->ops.gr.init.preemption_state != NULL) {