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gpu: nvgpu: fix MISRA violations in bitops unit

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Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset.  OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.

Jira NVGPU-3545

Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
ajesh
2019-06-03 16:39:32 +05:30
committed by mobile promotions
parent 57cee55ce7
commit a6cbfca58c
22 changed files with 158 additions and 101 deletions
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4
userspace/units/fifo/tsg/nvgpu-tsg.c
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@@ -327,9 +327,9 @@ static int test_tsg_bind_channel(struct unit_module *m,
/* ch already already active */
runlist = &f->active_runlist_info[tsg->runlist_id];
if (branches & F_TSG_BIND_CHANNEL_ACTIVE) {
set_bit((int)ch->chid, runlist->active_channels);
nvgpu_set_bit(ch->chid, runlist->active_channels);
} else {
clear_bit((int)ch->chid, runlist->active_channels);
nvgpu_clear_bit(ch->chid, runlist->active_channels);
}
g->ops.tsg.bind_channel =