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git://nv-tegra.nvidia.com/linux-nvgpu.git
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gpu: nvgpu: gv11b: enable devfreq
After moving devfreq enable to end of finalize power on, intermittent issues related to gpu booting with devfreq enabled are fixed. Enabled devfreq for gv11b by enabling ""nvhost_podgov" governor in platform data. Reused scaling functions from gp10b/gk20a. Removed emc floor on railgate for power saving. Added max emc frequency as floor in rail-ungate for faster gpu boot. Bug 2049965 Bug 2039013 Bug 200377508 Change-Id: Ia1dec278b663b9f7ed859dd953a60f3eae7ef9a0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1644702 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1,7 +1,7 @@
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/*
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* GP10B Tegra Platform Interface
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -97,7 +97,7 @@ int gp10b_tegra_get_clocks(struct device *dev)
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return 0;
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}
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static void gp10b_tegra_scale_init(struct device *dev)
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void gp10b_tegra_scale_init(struct device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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struct gk20a_scale_profile *profile = platform->g->scale_profile;
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@@ -265,7 +265,7 @@ int gp10b_tegra_reset_deassert(struct device *dev)
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return ret;
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}
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static void gp10b_tegra_prescale(struct device *dev)
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void gp10b_tegra_prescale(struct device *dev)
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{
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struct gk20a *g = get_gk20a(dev);
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u32 avg = 0;
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@@ -277,7 +277,7 @@ static void gp10b_tegra_prescale(struct device *dev)
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gk20a_dbg_fn("done");
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}
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static void gp10b_tegra_postscale(struct device *pdev,
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void gp10b_tegra_postscale(struct device *pdev,
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unsigned long freq)
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{
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struct gk20a_platform *platform = gk20a_get_platform(pdev);
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@@ -286,7 +286,7 @@ static void gp10b_tegra_postscale(struct device *pdev,
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unsigned long emc_rate;
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gk20a_dbg_fn("");
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if (profile && !gp10b_tegra_is_railgated(pdev)) {
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if (profile && !platform->is_railgated(pdev)) {
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unsigned long emc_scale;
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if (freq <= gp10b_freq_table[0])
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@@ -306,7 +306,7 @@ static void gp10b_tegra_postscale(struct device *pdev,
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gk20a_dbg_fn("done");
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}
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static long gp10b_round_clk_rate(struct device *dev, unsigned long rate)
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long gp10b_round_clk_rate(struct device *dev, unsigned long rate)
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{
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struct gk20a *g = get_gk20a(dev);
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struct gk20a_scale_profile *profile = g->scale_profile;
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@@ -321,7 +321,7 @@ static long gp10b_round_clk_rate(struct device *dev, unsigned long rate)
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return freq_table[max_states - 1];
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}
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static int gp10b_clk_get_freqs(struct device *dev,
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int gp10b_clk_get_freqs(struct device *dev,
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unsigned long **freqs, int *num_freqs)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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@@ -23,6 +23,7 @@
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#include <linux/reset.h>
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#include <linux/hashtable.h>
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#include <linux/clk.h>
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#include <linux/platform/tegra/emc_bwmgr.h>
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#include <nvgpu/nvhost.h>
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@@ -34,6 +35,7 @@
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#include "gk20a/gk20a.h"
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#include "platform_gk20a.h"
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#include "clk.h"
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#include "scale.h"
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#include "gp10b/platform_gp10b.h"
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#include "platform_gp10b_tegra.h"
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@@ -135,9 +137,16 @@ static int gv11b_tegra_railgate(struct device *dev)
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{
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#ifdef TEGRA194_POWER_DOMAIN_GPU
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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struct gk20a_scale_profile *profile = platform->g->scale_profile;
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struct gk20a *g = get_gk20a(dev);
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int i;
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/* remove emc frequency floor */
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if (profile)
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tegra_bwmgr_set_emc(
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(struct tegra_bwmgr_client *)profile->private_data,
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0, TEGRA_BWMGR_SET_EMC_FLOOR);
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if (tegra_bpmp_running()) {
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nvgpu_log(g, gpu_dbg_info, "bpmp running");
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if (!tegra_powergate_is_powered(TEGRA194_POWER_DOMAIN_GPU)) {
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@@ -164,6 +173,7 @@ static int gv11b_tegra_unrailgate(struct device *dev)
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#ifdef TEGRA194_POWER_DOMAIN_GPU
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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struct gk20a *g = get_gk20a(dev);
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struct gk20a_scale_profile *profile = platform->g->scale_profile;
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int i;
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if (tegra_bpmp_running()) {
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@@ -182,6 +192,13 @@ static int gv11b_tegra_unrailgate(struct device *dev)
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} else {
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nvgpu_log(g, gpu_dbg_info, "bpmp not running");
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}
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/* to start with set emc frequency floor to max rate*/
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if (profile)
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tegra_bwmgr_set_emc(
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(struct tegra_bwmgr_client *)profile->private_data,
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tegra_bwmgr_get_max_emc_rate(),
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TEGRA_BWMGR_SET_EMC_FLOOR);
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#endif
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return ret;
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}
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@@ -225,6 +242,17 @@ struct gk20a_platform gv11b_tegra_platform = {
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.busy = gk20a_tegra_busy,
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.idle = gk20a_tegra_idle,
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.clk_round_rate = gp10b_round_clk_rate,
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.get_clk_freqs = gp10b_clk_get_freqs,
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/* frequency scaling configuration */
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.initscale = gp10b_tegra_scale_init,
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.prescale = gp10b_tegra_prescale,
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.postscale = gp10b_tegra_postscale,
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.devfreq_governor = "nvhost_podgov",
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.qos_notify = gk20a_scale_qos_notify,
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.dump_platform_dependencies = gk20a_tegra_debug_dump,
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.soc_name = "tegra19x",
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@@ -1,7 +1,7 @@
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/*
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* GP10B Platform (SoC) Interface
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -30,5 +30,10 @@ struct device;
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int gp10b_tegra_get_clocks(struct device *dev);
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int gp10b_tegra_reset_assert(struct device *dev);
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int gp10b_tegra_reset_deassert(struct device *dev);
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void gp10b_tegra_scale_init(struct device *dev);
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long gp10b_round_clk_rate(struct device *dev, unsigned long rate);
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int gp10b_clk_get_freqs(struct device *dev,
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unsigned long **freqs, int *num_freqs);
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void gp10b_tegra_prescale(struct device *dev);
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void gp10b_tegra_postscale(struct device *pdev, unsigned long freq);
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#endif
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