gpu: nvgpu: vgpu: add t210 gm20b support

- add hal initializaiton
- create folders vgpu/gk20a and vgpu/gm20b for specific code

Bug 1653185

Change-Id: If94d45e22a1d73d2e4916673736cc29751be4e40
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/774148
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -74,7 +74,11 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
 	vgpu/ce2_vgpu.o \
 	vgpu/mm_vgpu.o \
 	vgpu/debug_vgpu.o \
-	vgpu/vgpu.o
+	vgpu/vgpu.o \
+	vgpu/gk20a/vgpu_hal_gk20a.o \
+	vgpu/gk20a/vgpu_gr_gk20a.o \
+	vgpu/gm20b/vgpu_hal_gm20b.o \
+	vgpu/gm20b/vgpu_gr_gm20b.o
 
 nvgpu-$(CONFIG_TEGRA_CLK_FRAMEWORK) += \
 	gm20b/clk_gm20b.o \

drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/kernel.h>
+
+#include "gk20a/hw_gr_gk20a.h"
+#include "gk20a/gk20a.h"
+#include "vgpu/vgpu.h"
+
+static void vgpu_gk20a_detect_sm_arch(struct gk20a *g)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(g->dev);
+	u32 v = 0, raw_version, version = 0;
+
+	gk20a_dbg_fn("");
+
+	if (vgpu_get_attribute(platform->virt_handle,
+			TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, &v))
+		gk20a_err(dev_from_gk20a(g), "failed to retrieve SM arch");
+
+	raw_version = gr_gpc0_tpc0_sm_arch_spa_version_v(v);
+
+	if (raw_version == gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v())
+		version = 0x320; /* SM 3.2 */
+	else
+		gk20a_err(dev_from_gk20a(g), "Unknown SM version 0x%x",
+			  raw_version);
+
+	/* on Kepler, SM version == SPA version */
+	g->gpu_characteristics.sm_arch_spa_version = version;
+	g->gpu_characteristics.sm_arch_sm_version = version;
+
+	g->gpu_characteristics.sm_arch_warp_count =
+		gr_gpc0_tpc0_sm_arch_warp_count_v(v);
+}
+
+void vgpu_gk20a_init_gr_ops(struct gpu_ops *gops)
+{
+	gops->gr.detect_sm_arch = vgpu_gk20a_detect_sm_arch;
+}

drivers/gpu/nvgpu/vgpu/gk20a/vgpu_gr_gk20a.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __VGPU_GR_GK20A_H__
+#define __VGPU_GR_GK20A_H__
+
+#include "gk20a/gk20a.h"
+
+void vgpu_gk20a_init_gr_ops(struct gpu_ops *gops);
+
+#endif

drivers/gpu/nvgpu/vgpu/gk20a/vgpu_hal_gk20a.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/hal_gk20a.h"
+#include "vgpu/vgpu.h"
+#include "vgpu_gr_gk20a.h"
+
+int vgpu_gk20a_init_hal(struct gk20a *g)
+{
+	int err;
+
+	err = gk20a_init_hal(g);
+	if (err)
+		return err;
+	vgpu_init_hal_common(g);
+	vgpu_gk20a_init_gr_ops(&g->ops);
+
+	return 0;
+}

drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/kernel.h>
+
+#include "gm20b/hw_gr_gm20b.h"
+#include "gk20a/gk20a.h"
+#include "vgpu/vgpu.h"
+
+static void vgpu_gm20b_detect_sm_arch(struct gk20a *g)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(g->dev);
+	u32 v = 0;
+
+	gk20a_dbg_fn("");
+
+	if (vgpu_get_attribute(platform->virt_handle,
+			TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, &v))
+		gk20a_err(dev_from_gk20a(g), "failed to retrieve SM arch");
+
+	g->gpu_characteristics.sm_arch_spa_version =
+		gr_gpc0_tpc0_sm_arch_spa_version_v(v);
+	g->gpu_characteristics.sm_arch_sm_version =
+		gr_gpc0_tpc0_sm_arch_sm_version_v(v);
+	g->gpu_characteristics.sm_arch_warp_count =
+		gr_gpc0_tpc0_sm_arch_warp_count_v(v);
+}
+
+void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops)
+{
+	gops->gr.detect_sm_arch = vgpu_gm20b_detect_sm_arch;
+}

drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __VGPU_GR_GM20B_H__
+#define __VGPU_GR_GM20B_H__
+
+#include "gk20a/gk20a.h"
+
+void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops);
+
+#endif

drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gm20b/hal_gm20b.h"
+#include "vgpu/vgpu.h"
+#include "vgpu_gr_gm20b.h"
+
+int vgpu_gm20b_init_hal(struct gk20a *g)
+{
+	int err;
+
+	err = gm20b_init_hal(g);
+	if (err)
+		return err;
+	vgpu_init_hal_common(g);
+	vgpu_gm20b_init_gr_ops(&g->ops);
+
+	return 0;
+}

drivers/gpu/nvgpu/vgpu/gr_vgpu.c

@@ -601,36 +601,18 @@ static int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
 	return 0;
 }
 
-static void vgpu_gr_detect_sm_arch(struct gk20a *g)
-{
-	struct gk20a_platform *platform = gk20a_get_platform(g->dev);
-	u32 v = 0, raw_version, version = 0;
-
-	gk20a_dbg_fn("");
-
-	if (vgpu_get_attribute(platform->virt_handle,
-			TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, &v))
-		gk20a_err(dev_from_gk20a(g), "failed to retrieve SM arch");
-
-	raw_version = gr_gpc0_tpc0_sm_arch_spa_version_v(v);
-	if (raw_version == gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v())
-		version = 0x320; /* SM 3.2 */
-	else
-		gk20a_err(dev_from_gk20a(g), "Unknown SM version 0x%x",
-			  raw_version);
-
-	/* on Kepler, SM version == SPA version */
-	g->gpu_characteristics.sm_arch_spa_version = version;
-	g->gpu_characteristics.sm_arch_sm_version = version;
-
-	g->gpu_characteristics.sm_arch_warp_count =
-		gr_gpc0_tpc0_sm_arch_warp_count_v(v);
-}
-
 static u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
-	/* One TPC for gk20a */
+	struct gk20a_platform *platform = gk20a_get_platform(g->dev);
-	return 0x1;
+	u32 data;
+
+	WARN_ON(gpc_index > 0);
+
+	if (vgpu_get_attribute(platform->virt_handle,
+			TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK, &data))
+		gk20a_err(dev_from_gk20a(g), "failed to retrieve gpc0_tpc_mask");
+
+	return data;
 }
 
 static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g)
@@ -661,6 +643,40 @@ static u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g)
 	return fbp_en_mask;
 }
 
+static u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(g->dev);
+	u32 val = 0;
+
+	gk20a_dbg_fn("");
+
+	if (vgpu_get_attribute(platform->virt_handle,
+			TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP, &val))
+		gk20a_err(dev_from_gk20a(g), "failed to retrieve max ltc per fbp");
+
+	return val;
+}
+
+static u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(g->dev);
+	u32 val = 0;
+
+	gk20a_dbg_fn("");
+
+	if (vgpu_get_attribute(platform->virt_handle,
+			TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC, &val))
+		gk20a_err(dev_from_gk20a(g), "failed to retrieve lts per ltc");
+
+	return val;
+}
+
+static u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g)
+{
+	/* no one use it yet */
+	return NULL;
+}
+
 static int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
 			   struct zbc_entry *zbc_val)
 {
@@ -875,10 +891,12 @@ void vgpu_init_gr_ops(struct gpu_ops *gops)
 	gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx;
 	gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull;
 	gops->gr.get_zcull_info = vgpu_gr_get_zcull_info;
-	gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch;
 	gops->gr.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask;
 	gops->gr.get_max_fbps_count = vgpu_gr_get_max_fbps_count;
 	gops->gr.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask;
+	gops->gr.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp;
+	gops->gr.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc;
+	gops->gr.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask;
 	gops->gr.zbc_set_table = vgpu_gr_add_zbc;
 	gops->gr.zbc_query_table = vgpu_gr_query_zbc;
 }

drivers/gpu/nvgpu/vgpu/ltc_vgpu.c

@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU L2
  *
- * Copyright (c) 2014 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -24,7 +24,7 @@ static int vgpu_determine_L2_size_bytes(struct gk20a *g)
 
 	if (vgpu_get_attribute(platform->virt_handle,
 			TEGRA_VGPU_ATTRIB_L2_SIZE, &cache_size))
-		dev_err(dev_from_gk20a(g), "unable to get L2 size");
+		dev_err(dev_from_gk20a(g), "unable to get L2 size\n");
 
 	return cache_size;
 }
@@ -33,11 +33,26 @@ static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
 {
 	struct gk20a_platform *platform = gk20a_get_platform(g->dev);
 	u32 max_comptag_lines = 0;
+	int err;
 
 	gk20a_dbg_fn("");
 
-	vgpu_get_attribute(platform->virt_handle,
+	err = vgpu_get_attribute(platform->virt_handle,
+			TEGRA_VGPU_ATTRIB_CACHELINE_SIZE,
+			&gr->cacheline_size);
+	err |= vgpu_get_attribute(platform->virt_handle,
+			TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE,
+			&gr->comptags_per_cacheline);
+	err |= vgpu_get_attribute(platform->virt_handle,
+			TEGRA_VGPU_ATTRIB_SLICES_PER_LTC,
+			&gr->slices_per_ltc);
+	err |= vgpu_get_attribute(platform->virt_handle,
 			TEGRA_VGPU_ATTRIB_COMPTAG_LINES, &max_comptag_lines);
+	if (err) {
+		dev_err(dev_from_gk20a(g), "failed to get ctags atributes\n");
+		return -ENXIO;
+	}
+
 	if (max_comptag_lines < 2)
 		return -ENXIO;
 
@@ -46,8 +61,23 @@ static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
 	return 0;
 }
 
+static void vgpu_ltc_init_fs_state(struct gk20a *g)
+{
+	struct gk20a_platform *platform = gk20a_get_platform(g->dev);
+	u32 ltc_count = 0;
+	int err;
+
+	gk20a_dbg_fn("");
+
+	err = vgpu_get_attribute(platform->virt_handle,
+			TEGRA_VGPU_ATTRIB_LTC_COUNT, &ltc_count);
+	WARN_ON(err);
+	g->ltc_count = ltc_count;
+}
+
 void vgpu_init_ltc_ops(struct gpu_ops *gops)
 {
 	gops->ltc.determine_L2_size_bytes = vgpu_determine_L2_size_bytes;
 	gops->ltc.init_comptags = vgpu_ltc_init_comptags;
+	gops->ltc.init_fs_state = vgpu_ltc_init_fs_state;
 }

drivers/gpu/nvgpu/vgpu/mm_vgpu.c

@@ -282,6 +282,7 @@ static int vgpu_vm_alloc_share(struct gk20a_as_share *as_share,
 	msg.cmd = TEGRA_VGPU_CMD_AS_ALLOC_SHARE;
 	msg.handle = platform->virt_handle;
 	p->size = vm->va_limit;
+	p->big_page_size = vm->big_page_size;
 	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
 	if (err || msg.ret) {
 		err = -ENOMEM;

drivers/gpu/nvgpu/vgpu/vgpu.c

@@ -22,6 +22,8 @@
 #include "gk20a/hal_gk20a.h"
 #include "gk20a/hw_mc_gk20a.h"
 
+#include "gm20b/hal_gm20b.h"
+
 static inline int vgpu_comm_init(struct platform_device *pdev)
 {
 	size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES };
@@ -243,27 +245,38 @@ static void vgpu_detect_chip(struct gk20a *g)
 			g->gpu_characteristics.rev);
 }
 
+void vgpu_init_hal_common(struct gk20a *g)
+{
+	struct gpu_ops *gops = &g->ops;
+
+	vgpu_init_fifo_ops(gops);
+	vgpu_init_gr_ops(gops);
+	vgpu_init_ltc_ops(gops);
+	vgpu_init_mm_ops(gops);
+	vgpu_init_debug_ops(gops);
+}
+
 static int vgpu_init_hal(struct gk20a *g)
 {
 	u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
+	int err;
 
 	switch (ver) {
 	case GK20A_GPUID_GK20A:
 		gk20a_dbg_info("gk20a detected");
-		/* init gk20a ops then override with virt extensions */
+		err = vgpu_gk20a_init_hal(g);
-		gk20a_init_hal(g);
+		break;
-		vgpu_init_fifo_ops(&g->ops);
+	case GK20A_GPUID_GM20B:
-		vgpu_init_gr_ops(&g->ops);
+		gk20a_dbg_info("gm20b detected");
-		vgpu_init_ltc_ops(&g->ops);
+		err = vgpu_gm20b_init_hal(g);
-		vgpu_init_mm_ops(&g->ops);
-		vgpu_init_debug_ops(&g->ops);
 		break;
 	default:
 		gk20a_err(&g->dev->dev, "no support for %x", ver);
-		return -ENODEV;
+		err = -ENODEV;
+		break;
 	}
 
-	return 0;
+	return err;
 }
 
 int vgpu_pm_finalize_poweron(struct device *dev)

drivers/gpu/nvgpu/vgpu/vgpu.h

@@ -46,6 +46,10 @@ int vgpu_init_fifo_support(struct gk20a *g);
 int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
 int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
 		size_t size_out);
+
+void vgpu_init_hal_common(struct gk20a *g);
+int vgpu_gk20a_init_hal(struct gk20a *g);
+int vgpu_gm20b_init_hal(struct gk20a *g);
 #else
 static inline int vgpu_pm_prepare_poweroff(struct device *dev)
 {

include/linux/tegra_vgpu.h

@@ -89,7 +89,14 @@ enum {
 	TEGRA_VGPU_ATTRIB_L2_SIZE,
 	TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH,
 	TEGRA_VGPU_ATTRIB_NUM_FBPS,
-	TEGRA_VGPU_ATTRIB_FBP_EN_MASK
+	TEGRA_VGPU_ATTRIB_FBP_EN_MASK,
+	TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP,
+	TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC,
+	TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK,
+	TEGRA_VGPU_ATTRIB_CACHELINE_SIZE,
+	TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE,
+	TEGRA_VGPU_ATTRIB_SLICES_PER_LTC,
+	TEGRA_VGPU_ATTRIB_LTC_COUNT
 };
 
 struct tegra_vgpu_attrib_params {
@@ -100,6 +107,7 @@ struct tegra_vgpu_attrib_params {
 struct tegra_vgpu_as_share_params {
 	u64 size;
 	u64 handle;
+	u32 big_page_size;
 };
 
 struct tegra_vgpu_as_bind_share_params {