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gpu: nvgpu: wakeup semaphores after clearing CE2 interrupt

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In gk20a_ce2_nonstall_isr(), we first invoke semaphore workqueue
on all channels and then clear the interrupt
This delay in clearing the interrupt can sometimes lead to
dropping of new interrupt

If that happens, we never invoke gk20a_channel_semaphore_wakeup()
for new semaphore interrupts and semaphore waiting
never completes.

Fix this by moving gk20a_channel_semaphore_wakeup() after
we clear the interrupt

Bug 200131938

Change-Id: I26d72f04a8b49f4a3ac326bf6037cd04c741a920
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/784771
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2015-08-17 16:19:09 +05:30
committed by Terje Bergstrom
parent 2b0e5ed361
commit db8bce518b
1 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
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@@ -41,8 +41,6 @@ static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
{
gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
/* wake theads waiting in this channel */
gk20a_channel_semaphore_wakeup(g);
return ce2_intr_status_nonblockpipe_pending_f();
}
@@ -81,14 +79,16 @@ void gk20a_ce2_isr(struct gk20a *g)
void gk20a_ce2_nonstall_isr(struct gk20a *g)
{
u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
u32 clear_intr = 0;
gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f())
clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr);
if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) {
gk20a_writel(g, ce2_intr_status_r(),
ce2_nonblockpipe_isr(g, ce2_intr));
gk20a_writel(g, ce2_intr_status_r(), clear_intr);
/* wake threads waiting in this channel */
gk20a_channel_semaphore_wakeup(g);
}
return;
}