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gpu: nvgpu: vgpu: added VAB support for HV

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Added below IVC commands to support VAB on HV.

 * TEGRA_VGPU_CMD_FB_VAB_RESERVE - Enable & Configure VAB tracking
 * TEGRA_VGPU_CMD_FB_VAB_FLUSH_STATE - Dump VAB to user buffer
 * TEGRA_VGPU_CMD_FB_VAB_RELEASE - Disable VAB tracking

Also set HAL and enable VAB for ga10b vgpu.

Jira GVSCI-4619

Change-Id: Id7564611c24740ab8613e4baa420ee58fb52759a
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2507268
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kadamati
2021-03-29 19:30:16 +05:30
committed by mobile promotions
parent 3ad1db2bb6
commit aabc161151
8 changed files with 186 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/nvgpu-vgpu.yaml
View File

@@ -59,6 +59,8 @@ all:
common/vgpu/fbp/fbp_vgpu.h,
common/vgpu/fb/fb_vgpu.c,
common/vgpu/fb/fb_vgpu.h,
common/vgpu/fb/vab_vgpu.c,
common/vgpu/fb/vab_vgpu.h,
common/vgpu/intr/intr_vgpu.c,
common/vgpu/intr/intr_vgpu.h,
common/vgpu/ivc/comm_vgpu.c,

1
drivers/gpu/nvgpu/Makefile
View File

@@ -613,6 +613,7 @@ nvgpu-$(CONFIG_NVGPU_GR_VIRTUALIZATION) += \
common/vgpu/ltc/ltc_vgpu.o \
common/vgpu/fbp/fbp_vgpu.o \
common/vgpu/fb/fb_vgpu.o \
common/vgpu/fb/vab_vgpu.o \
common/vgpu/gr/gr_vgpu.o \
common/vgpu/gr/ctx_vgpu.o \
common/vgpu/gr/subctx_vgpu.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -585,6 +585,7 @@ srcs += common/vgpu/init/init_vgpu.c \
common/vgpu/mm/vm_vgpu.c \
common/vgpu/gr/gr_vgpu.c \
common/vgpu/fb/fb_vgpu.c \
common/vgpu/fb/vab_vgpu.c \
common/vgpu/gr/ctx_vgpu.c \
common/vgpu/gr/subctx_vgpu.c \
common/vgpu/clk_vgpu.c \

126
drivers/gpu/nvgpu/common/vgpu/fb/vab_vgpu.c Normal file
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@@ -0,0 +1,126 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/string.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/vgpu/vgpu.h>
#include <nvgpu/vgpu/vgpu_ivc.h>
#include <nvgpu/vgpu/tegra_vgpu.h>
#include "common/vgpu/ivc/comm_vgpu.h"
#include "vab_vgpu.h"
int vgpu_fb_vab_reserve(struct gk20a *g, u32 vab_mode, u32 num_range_checkers,
struct nvgpu_vab_range_checker *vab_range_checker)
{
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_fb_vab_reserve_params *p = &msg.params.fb_vab_reserve;
int err;
void *oob;
void *oob_handle;
size_t size, oob_size;
oob_handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
TEGRA_VGPU_QUEUE_CMD, &oob, &oob_size);
if (!oob_handle) {
return -EINVAL;
}
size = sizeof(*vab_range_checker) * num_range_checkers;
if (oob_size < size) {
err = -ENOMEM;
goto done;
}
msg.cmd = TEGRA_VGPU_CMD_FB_VAB_RESERVE;
msg.handle = vgpu_get_handle(g);
p->vab_mode = vab_mode;
p->num_range_checkers = num_range_checkers;
nvgpu_memcpy((u8 *)oob, (u8 *)vab_range_checker, size);
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err != 0 ? err : msg.ret;
if (err != 0) {
nvgpu_err(g, "fb vab reserve failed err %d", err);
}
done:
vgpu_ivc_oob_put_ptr(oob_handle);
return err;
}
int vgpu_fb_vab_dump_and_clear(struct gk20a *g, u64 *user_buf,
u64 user_buf_size)
{
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_fb_vab_dump_and_clear_params *p =
&msg.params.fb_vab_dump_and_clear;
int err;
void *oob;
void *oob_handle;
size_t oob_size;
oob_handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(),
TEGRA_VGPU_QUEUE_CMD, &oob, &oob_size);
if (!oob_handle) {
return -EINVAL;
}
if (oob_size < user_buf_size) {
err = -ENOMEM;
goto done;
}
msg.cmd = TEGRA_VGPU_CMD_FB_VAB_DUMP_CLEAR;
msg.handle = vgpu_get_handle(g);
p->user_buf_size = user_buf_size;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err != 0 ? err : msg.ret;
if (err == 0) {
nvgpu_memcpy((u8 *)user_buf, (u8 *)oob, user_buf_size);
} else {
nvgpu_err(g, "fb vab flush state failed err %d", err);
}
done:
vgpu_ivc_oob_put_ptr(oob_handle);
return err;
}
int vgpu_fb_vab_release(struct gk20a *g)
{
struct tegra_vgpu_cmd_msg msg = {};
int err;
msg.cmd = TEGRA_VGPU_CMD_FB_VAB_RELEASE;
msg.handle = vgpu_get_handle(g);
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err != 0 ? err : msg.ret;
if (err != 0) {
nvgpu_err(g, "fb vab release failed err %d", err);
}
return err;
}

27
drivers/gpu/nvgpu/common/vgpu/fb/vab_vgpu.h Normal file
View File

@@ -0,0 +1,27 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
int vgpu_fb_vab_reserve(struct gk20a *g, u32 vab_mode, u32 num_range_checkers,
struct nvgpu_vab_range_checker *vab_range_checker);
int vgpu_fb_vab_dump_and_clear(struct gk20a *g, u64 *user_buf,
u64 user_buf_size);
int vgpu_fb_vab_release(struct gk20a *g);

4
drivers/gpu/nvgpu/hal/fb/vab/vab_ga10b.c
View File

@@ -99,7 +99,7 @@ static int ga10b_fb_vab_config_address_range(struct gk20a *g,
u32 granularity_shift_bits = 0U;
int err = 0U;
nvgpu_err(g, " ");
nvgpu_log_fn(g, " ");
g->mm.vab.user_num_range_checkers = num_range_checkers;
nvgpu_log(g, gpu_dbg_vab, "num_range_checkers %u", num_range_checkers);
@@ -332,7 +332,7 @@ int ga10b_fb_vab_release(struct gk20a *g)
u32 vab_buf_size_reg = 0U;
u32 vab_reg = 0U;
nvgpu_err(g, " ");
nvgpu_log_fn(g, " ");
vab_buf_size_reg = nvgpu_readl(g,
fb_mmu_vidmem_access_bit_buffer_size_r());

13
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
View File

@@ -134,6 +134,7 @@
#include "common/vgpu/init/init_vgpu.h"
#include "common/vgpu/fb/fb_vgpu.h"
#include "common/vgpu/fb/vab_vgpu.h"
#include "common/vgpu/top/top_vgpu.h"
#include "common/vgpu/fifo/fifo_vgpu.h"
#include "common/vgpu/fifo/channel_vgpu.h"
@@ -204,6 +205,7 @@ static int vgpu_ga10b_init_gpu_characteristics(struct gk20a *g)
nvgpu_set_enabled(g, NVGPU_SUPPORT_PROFILER_V2_DEVICE, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_PROFILER_V2_CONTEXT, false);
nvgpu_set_enabled(g, NVGPU_SUPPORT_SMPC_GLOBAL_MODE, true);
nvgpu_set_enabled(g, NVGPU_SUPPORT_VAB_ENABLED, true);
#endif
return 0;
@@ -454,6 +456,8 @@ static const struct gops_gr_intr vgpu_ga10b_ops_gr_intr = {
static const struct gops_gr vgpu_ga10b_ops_gr = {
.gr_init_support = nvgpu_gr_init_support,
.gr_suspend = nvgpu_gr_suspend,
.vab_init = NULL,
.vab_release = NULL,
#ifdef CONFIG_NVGPU_DEBUGGER
.set_alpha_circular_buffer_size = NULL,
.set_circular_buffer_size = NULL,
@@ -1045,6 +1049,14 @@ static const struct gops_grmgr vgpu_ga10b_ops_grmgr = {
.init_gr_manager = nvgpu_init_gr_manager,
};
static const struct gops_fb_vab vgpu_ga10b_ops_fb_vab = {
.init = NULL,
.reserve = vgpu_fb_vab_reserve,
.dump_and_clear = vgpu_fb_vab_dump_and_clear,
.release = vgpu_fb_vab_release,
.teardown = NULL,
};
int vgpu_ga10b_init_hal(struct gk20a *g)
{
struct gpu_ops *gops = &g->ops;
@@ -1080,6 +1092,7 @@ int vgpu_ga10b_init_hal(struct gk20a *g)
gops->gpu_class = vgpu_ga10b_ops_gpu_class;
gops->fb = vgpu_ga10b_ops_fb;
gops->fb.intr = vgpu_ga10b_ops_fb_intr;
gops->fb.vab = vgpu_ga10b_ops_fb_vab;
gops->cg = vgpu_ga10b_ops_cg;
gops->fifo = vgpu_ga10b_ops_fifo;
gops->engine = vgpu_ga10b_ops_engine;

14
drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
View File

@@ -119,6 +119,9 @@ enum {
TEGRA_VGPU_CMD_PERF_UPDATE_GET_PUT = 95,
TEGRA_VGPU_CMD_ALLOC_OBJ_CTX = 96,
TEGRA_VGPU_CMD_SET_PREEMPTION_MODE = 97,
TEGRA_VGPU_CMD_FB_VAB_RESERVE = 98,
TEGRA_VGPU_CMD_FB_VAB_DUMP_CLEAR = 99,
TEGRA_VGPU_CMD_FB_VAB_RELEASE = 100,
};
struct tegra_vgpu_connect_params {
@@ -658,6 +661,15 @@ struct tegra_vgpu_preemption_mode_params {
u32 compute_preempt_mode;
};
struct tegra_vgpu_fb_vab_reserve_params {
u32 vab_mode;
u32 num_range_checkers;
};
struct tegra_vgpu_fb_vab_dump_and_clear_params {
u64 user_buf_size;
};
struct tegra_vgpu_cmd_msg {
u32 cmd;
int ret;
@@ -720,6 +732,8 @@ struct tegra_vgpu_cmd_msg {
struct tegra_vgpu_set_sm_exception_type_mask_params set_sm_exception_mask;
struct tegra_vgpu_get_tpc_exception_en_status_params get_tpc_exception_status;
struct tegra_vgpu_fb_set_mmu_debug_mode_params fb_set_mmu_debug_mode;
struct tegra_vgpu_fb_vab_reserve_params fb_vab_reserve;
struct tegra_vgpu_fb_vab_dump_and_clear_params fb_vab_dump_and_clear;
struct tegra_vgpu_gr_set_mmu_debug_mode_params gr_set_mmu_debug_mode;
struct tegra_vgpu_perfbuf_inst_block_mgt_params perfbuf_inst_block_management;
struct tegra_vgpu_l2_max_ways_evict_last_params l2_max_ways_evict_last;