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gpu: nvgpu: channel: use u32 for syncpt id

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Make the APIs nvgpu_channel_sync_get_syncpt_id() and
channel_sync_syncpt_get_id() return u32s rather than converting to
ints and back.

Also define FIFO_INVAL_SYNCPT_ID to use for invalid syncpt IDs rather
than using magic numbers.

JIRA NVGPU-1008

Change-Id: I4dde6b15fd3708fb0126b46c6fea8ac1b447c7ce
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014821
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-02-08 10:22:32 -05:00
committed by mobile promotions
parent fa81cf9000
commit ab5684ce1b
6 changed files with 13 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c
View File

@@ -307,7 +307,7 @@ static void channel_sync_syncpt_set_safe_state(struct nvgpu_channel_sync *s)
nvgpu_nvhost_syncpt_set_safe_state(sp->nvhost_dev, sp->id); nvgpu_nvhost_syncpt_set_safe_state(sp->nvhost_dev, sp->id);
} }
static int channel_sync_syncpt_get_id(struct nvgpu_channel_sync_syncpt *sp) static u32 channel_sync_syncpt_get_id(struct nvgpu_channel_sync_syncpt *sp)
{ {
return sp->id; return sp->id;
} }
@@ -330,7 +330,7 @@ static void channel_sync_syncpt_destroy(struct nvgpu_channel_sync *s)
nvgpu_kfree(sp->c->g, sp); nvgpu_kfree(sp->c->g, sp);
} }
int nvgpu_channel_sync_get_syncpt_id(struct nvgpu_channel_sync_syncpt *s) u32 nvgpu_channel_sync_get_syncpt_id(struct nvgpu_channel_sync_syncpt *s)
{ {
return channel_sync_syncpt_get_id(s); return channel_sync_syncpt_get_id(s);
} }

2
drivers/gpu/nvgpu/gk20a/fence_gk20a.c
View File

@@ -199,7 +199,7 @@ void gk20a_init_fence(struct gk20a_fence *f,
return; return;
} }
f->ops = ops; f->ops = ops;
f->syncpt_id = -1; f->syncpt_id = FIFO_INVAL_SYNCPT_ID;
f->semaphore = NULL; f->semaphore = NULL;
f->os_fence = os_fence; f->os_fence = os_fence;
} }

1
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -44,6 +44,7 @@ struct tsg_gk20a;
#define FIFO_INVAL_CHANNEL_ID (~U32(0U)) #define FIFO_INVAL_CHANNEL_ID (~U32(0U))
#define FIFO_INVAL_TSG_ID (~U32(0U)) #define FIFO_INVAL_TSG_ID (~U32(0U))
#define FIFO_INVAL_RUNLIST_ID (~U32(0U)) #define FIFO_INVAL_RUNLIST_ID (~U32(0U))
#define FIFO_INVAL_SYNCPT_ID (~U32(0U))
#define ID_TYPE_CHANNEL 0U #define ID_TYPE_CHANNEL 0U
#define ID_TYPE_TSG 1U #define ID_TYPE_TSG 1U

5
drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
View File

@@ -157,9 +157,10 @@ int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
if (c->sync != NULL) { if (c->sync != NULL) {
sync_syncpt = nvgpu_channel_sync_to_syncpt(c->sync); sync_syncpt = nvgpu_channel_sync_to_syncpt(c->sync);
if (sync_syncpt != NULL) { if (sync_syncpt != NULL) {
new_syncpt = nvgpu_channel_sync_get_syncpt_id(sync_syncpt); new_syncpt =
nvgpu_channel_sync_get_syncpt_id(sync_syncpt);
} else { } else {
new_syncpt = -EINVAL; new_syncpt = FIFO_INVAL_SYNCPT_ID;
} }
} }
if ((new_syncpt != 0U) && (new_syncpt != old_syncpt)) { if ((new_syncpt != 0U) && (new_syncpt != old_syncpt)) {

8
drivers/gpu/nvgpu/include/nvgpu/channel_sync_syncpt.h
View File

@@ -2,7 +2,7 @@
* *
* Nvgpu Channel Synchronization Abstraction (Syncpoints) * Nvgpu Channel Synchronization Abstraction (Syncpoints)
* *
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -38,7 +38,7 @@ struct nvgpu_channel_sync_syncpt;
/* /*
* Returns the sync point id or negative number if no syncpt * Returns the sync point id or negative number if no syncpt
*/ */
int nvgpu_channel_sync_get_syncpt_id(struct nvgpu_channel_sync_syncpt *s); u32 nvgpu_channel_sync_get_syncpt_id(struct nvgpu_channel_sync_syncpt *s);
/* /*
* Returns the sync point address of sync point or 0 if not supported * Returns the sync point address of sync point or 0 if not supported
@@ -69,10 +69,10 @@ nvgpu_channel_sync_syncpt_create(struct channel_gk20a *c,
#else #else
static inline int nvgpu_channel_sync_get_syncpt_id( static inline u32 nvgpu_channel_sync_get_syncpt_id(
struct nvgpu_channel_sync_syncpt *s) struct nvgpu_channel_sync_syncpt *s)
{ {
return -EINVAL; return FIFO_INVAL_SYNCPT_ID;
} }
static inline u64 nvgpu_channel_sync_get_syncpt_address( static inline u64 nvgpu_channel_sync_get_syncpt_address(
struct nvgpu_channel_sync_syncpt *s) struct nvgpu_channel_sync_syncpt *s)

4
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2011-2018, NVIDIA Corporation. All rights reserved. * Copyright (c) 2011-2019, NVIDIA Corporation. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@@ -443,7 +443,7 @@ static int gk20a_ctrl_prepare_compressible_read(
args->fence.syncpt_value = args->fence.syncpt_value =
fence_out->syncpt_value; fence_out->syncpt_value;
} else { } else {
args->fence.syncpt_id = -1; args->fence.syncpt_id = FIFO_INVAL_SYNCPT_ID;
args->fence.syncpt_value = 0; args->fence.syncpt_value = 0;
} }
} }