gpu: nvgpu: use HAL to read fecs_ctx_state_store_major_rev_id()

In gk20a/gr_ctx_gk20a.c we right now directly read the GR register
gr_fecs_ctx_state_store_major_rev_id_r() which adds the dependency
to GR h/w header

Add a new HAL g.ops.gr.get_fecs_ctx_state_store_major_rev_id() to
read this register and use this instead
Also remove h/w header from gr_ctx_gk20a.c

Jira NVGPU-1317

Change-Id: Iab64fbfacff4d7ce4f3b61ca90b00ddc77e29551
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936453
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c

@@ -32,8 +32,6 @@
 
 #include "gr_ctx_gk20a.h"
 
-#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
-
 static int gr_gk20a_alloc_load_netlist_u32(struct gk20a *g, u32 *src, u32 len,
 			struct u32_list_gk20a *u32_list)
 {
@@ -104,8 +102,7 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr)
 	} else {
 		net = NETLIST_SLOT_A;
 		max = MAX_NETLIST;
-		major_v_hw = gk20a_readl(g,
-				gr_fecs_ctx_state_store_major_rev_id_r());
+		major_v_hw = g->ops.gr.get_fecs_ctx_state_store_major_rev_id(g);
 		g->gr.ctx_vars.dynamic = true;
 	}
 

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -8890,3 +8890,8 @@ void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr)
 		GR_CHANNEL_MAP_TLB_SIZE);
 	nvgpu_spinlock_release(&gr->ch_tlb_lock);
 }
+
+u32 gk20a_gr_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g)
+{
+	return nvgpu_readl(g, gr_fecs_ctx_state_store_major_rev_id_r());
+}

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -838,4 +838,6 @@ void gk20a_gr_destroy_ctx_buffer(struct gk20a *g,
 int gk20a_gr_alloc_ctx_buffer(struct gk20a *g,
 	struct gr_ctx_buffer_desc *desc, size_t size);
 void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr);
+
+u32 gk20a_gr_get_fecs_ctx_state_store_major_rev_id(struct gk20a *g);
 #endif /*__GR_GK20A_H__*/

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -331,6 +331,8 @@ static const struct gpu_ops gm20b_ops = {
 			gr_gk20a_get_offset_in_gpccs_segment,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.dump_gr_falcon_stats = gk20a_fecs_dump_falcon_stats,
+		.get_fecs_ctx_state_store_major_rev_id =
+			gk20a_gr_get_fecs_ctx_state_store_major_rev_id,
 	},
 	.fb = {
 		.init_hw = gm20b_fb_init_hw,

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -407,6 +407,8 @@ static const struct gpu_ops gp106_ops = {
 			gr_gk20a_get_offset_in_gpccs_segment,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.dump_gr_falcon_stats = gk20a_fecs_dump_falcon_stats,
+		.get_fecs_ctx_state_store_major_rev_id =
+			gk20a_gr_get_fecs_ctx_state_store_major_rev_id,
 	},
 	.fb = {
 		.init_hw = gm20b_fb_init_hw,

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -368,6 +368,8 @@ static const struct gpu_ops gp10b_ops = {
 			gr_gk20a_get_offset_in_gpccs_segment,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.dump_gr_falcon_stats = gk20a_fecs_dump_falcon_stats,
+		.get_fecs_ctx_state_store_major_rev_id =
+			gk20a_gr_get_fecs_ctx_state_store_major_rev_id,
 	},
 	.fb = {
 		.init_hw = gm20b_fb_init_hw,

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -490,6 +490,8 @@ static const struct gpu_ops gv100_ops = {
 			gr_gk20a_get_offset_in_gpccs_segment,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.dump_gr_falcon_stats = gk20a_fecs_dump_falcon_stats,
+		.get_fecs_ctx_state_store_major_rev_id =
+			gk20a_gr_get_fecs_ctx_state_store_major_rev_id,
 	},
 	.fb = {
 		.init_hw = gv11b_fb_init_hw,

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -450,6 +450,8 @@ static const struct gpu_ops gv11b_ops = {
 			gr_gk20a_get_offset_in_gpccs_segment,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.dump_gr_falcon_stats = gk20a_fecs_dump_falcon_stats,
+		.get_fecs_ctx_state_store_major_rev_id =
+			gk20a_gr_get_fecs_ctx_state_store_major_rev_id,
 	},
 	.fb = {
 		.init_hw = gv11b_fb_init_hw,

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -526,6 +526,7 @@ struct gpu_ops {
 			u32 *__offset_in_segment);
 		void (*set_debug_mode)(struct gk20a *g, bool enable);
 		void (*dump_gr_falcon_stats)(struct gk20a *g);
+		u32 (*get_fecs_ctx_state_store_major_rev_id)(struct gk20a *g);
 	} gr;
 	struct {
 		void (*init_hw)(struct gk20a *g);

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -508,6 +508,8 @@ static const struct gpu_ops tu104_ops = {
 			gr_tu104_get_offset_in_gpccs_segment,
 		.set_debug_mode = gm20b_gr_set_debug_mode,
 		.dump_gr_falcon_stats = gk20a_fecs_dump_falcon_stats,
+		.get_fecs_ctx_state_store_major_rev_id =
+			gk20a_gr_get_fecs_ctx_state_store_major_rev_id,
 	},
 	.fb = {
 		.init_hw = gv11b_fb_init_hw,