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gpu: nvgpu: consolidate FALCON_ID macros

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Same Falcon IDs were defined in acr_lsfm.h with additional
defines. Update definitions in falcon.h and remove from
acr_lsfm.h.

JIRA NVGPU-1459

Change-Id: Id08c7f7a16c36087984a4418ddf7f4921084971a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1964438
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2018-12-03 11:53:41 +05:30
committed by mobile promotions
parent bcfce1af62
commit ac3cb4cc53
15 changed files with 61 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/nvgpu/common/pmu/acr_gm20b.c
View File

@@ -130,7 +130,7 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
}
nvgpu_memcpy((u8 *)lsf_desc, (u8 *)pmu_sig->data,
min_t(size_t, sizeof(*lsf_desc), pmu_sig->size));
lsf_desc->falcon_id = LSF_FALCON_ID_PMU;
lsf_desc->falcon_id = FALCON_ID_PMU;
p_img->desc = pmu->desc;
p_img->data = pmu->ucode_image;
@@ -170,7 +170,7 @@ static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
}
nvgpu_memcpy((u8 *)lsf_desc, (u8 *)fecs_sig->data,
min_t(size_t, sizeof(*lsf_desc), fecs_sig->size));
lsf_desc->falcon_id = LSF_FALCON_ID_FECS;
lsf_desc->falcon_id = FALCON_ID_FECS;
p_img->desc = nvgpu_kzalloc(g, sizeof(struct pmu_ucode_desc));
if (p_img->desc == NULL) {
@@ -242,7 +242,7 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
}
nvgpu_memcpy((u8 *)lsf_desc, (u8 *)gpccs_sig->data,
min_t(size_t, sizeof(*lsf_desc), gpccs_sig->size));
lsf_desc->falcon_id = LSF_FALCON_ID_GPCCS;
lsf_desc->falcon_id = FALCON_ID_GPCCS;
p_img->desc = nvgpu_kzalloc(g, sizeof(struct pmu_ucode_desc));
if (p_img->desc == NULL) {
@@ -298,10 +298,10 @@ bool gm20b_is_lazy_bootstrap(u32 falcon_id)
bool enable_status = false;
switch (falcon_id) {
case LSF_FALCON_ID_FECS:
case FALCON_ID_FECS:
enable_status = false;
break;
case LSF_FALCON_ID_GPCCS:
case FALCON_ID_GPCCS:
enable_status = false;
break;
default:
@@ -316,10 +316,10 @@ bool gm20b_is_priv_load(u32 falcon_id)
bool enable_status = false;
switch (falcon_id) {
case LSF_FALCON_ID_FECS:
case FALCON_ID_FECS:
enable_status = false;
break;
case LSF_FALCON_ID_GPCCS:
case FALCON_ID_GPCCS:
enable_status = false;
break;
default:
@@ -753,7 +753,7 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm,
}
/* Tag the terminator WPR header with an invalid falcon ID. */
last_wpr_hdr.falcon_id = LSF_FALCON_ID_INVALID;
last_wpr_hdr.falcon_id = FALCON_ID_INVALID;
nvgpu_mem_wr_n(g, ucode,
(u32)plsfm->managed_flcn_cnt *
(u32)sizeof(struct lsf_wpr_header),
@@ -942,7 +942,7 @@ static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm)
while (cnt != 0U) {
mg_ucode_img = plsfm->ucode_img_list;
if (mg_ucode_img->ucode_img.lsf_desc->falcon_id ==
LSF_FALCON_ID_PMU) {
FALCON_ID_PMU) {
lsfm_free_ucode_img_res(g, &mg_ucode_img->ucode_img);
} else {
lsfm_free_nonpmu_ucode_img_res(g,
@@ -1017,7 +1017,7 @@ static int lsf_gen_wpr_requirements(struct gk20a *g, struct ls_flcn_mgr *plsfm)
/* Finally, update ucode surface size to include updates */
pnode->full_ucode_size = wpr_offset -
pnode->lsb_header.ucode_off;
if (pnode->wpr_header.falcon_id != LSF_FALCON_ID_PMU) {
if (pnode->wpr_header.falcon_id != FALCON_ID_PMU) {
pnode->lsb_header.app_code_off =
pnode->lsb_header.bl_code_size;
pnode->lsb_header.app_code_size =
@@ -1419,7 +1419,7 @@ void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
acr->g = g;
acr->bootstrap_owner = LSF_FALCON_ID_PMU;
acr->bootstrap_owner = FALCON_ID_PMU;
acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
gm20b_acr_default_sw_init(g, &acr->acr);

18
drivers/gpu/nvgpu/common/pmu/acr_gp106.c
View File

@@ -162,7 +162,7 @@ int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
}
nvgpu_memcpy((u8 *)lsf_desc, (u8 *)pmu_sig->data,
min_t(size_t, sizeof(*lsf_desc), pmu_sig->size));
lsf_desc->falcon_id = LSF_FALCON_ID_PMU;
lsf_desc->falcon_id = FALCON_ID_PMU;
p_img->desc = pmu->desc_v1;
p_img->data = pmu->ucode_image;
@@ -233,7 +233,7 @@ int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
}
nvgpu_memcpy((u8 *)lsf_desc, (u8 *)fecs_sig->data,
min_t(size_t, sizeof(*lsf_desc), fecs_sig->size));
lsf_desc->falcon_id = LSF_FALCON_ID_FECS;
lsf_desc->falcon_id = FALCON_ID_FECS;
p_img->desc = nvgpu_kzalloc(g, sizeof(struct pmu_ucode_desc_v1));
if (p_img->desc == NULL) {
@@ -335,7 +335,7 @@ int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
}
nvgpu_memcpy((u8 *)lsf_desc, gpccs_sig->data,
min_t(size_t, sizeof(*lsf_desc), gpccs_sig->size));
lsf_desc->falcon_id = LSF_FALCON_ID_GPCCS;
lsf_desc->falcon_id = FALCON_ID_GPCCS;
p_img->desc = nvgpu_kzalloc(g, sizeof(struct pmu_ucode_desc_v1));
if (p_img->desc == NULL) {
@@ -432,7 +432,7 @@ int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
nvgpu_memcpy((u8 *)lsf_desc, (u8 *)sec2_sig->data,
min_t(size_t, sizeof(*lsf_desc), sec2_sig->size));
lsf_desc->falcon_id = LSF_FALCON_ID_SEC2;
lsf_desc->falcon_id = FALCON_ID_SEC2;
p_img->desc = desc;
p_img->data = ucode_image;
@@ -788,7 +788,7 @@ int gp106_flcn_populate_bl_dmem_desc(struct gk20a *g,
(void) memset((void *) ldr_cfg, 0,
sizeof(struct flcn_bl_dmem_desc_v1));
if (falconid == LSF_FALCON_ID_SEC2) {
if (falconid == FALCON_ID_SEC2) {
addr_code = addr_base + desc->app_start_offset;
ldr_cfg->ctx_dma = NV_SEC2_DMAIDX_UCODE;
ldr_cfg->non_sec_code_off = desc->app_resident_code_offset;
@@ -957,7 +957,7 @@ void lsfm_init_wpr_contents(struct gk20a *g,
}
/* Tag the terminator WPR header with an invalid falcon ID. */
last_wpr_hdr.falcon_id = LSF_FALCON_ID_INVALID;
last_wpr_hdr.falcon_id = FALCON_ID_INVALID;
tmp = plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header_v1);
nvgpu_assert(tmp <= U32_MAX);
nvgpu_mem_wr_n(g, ucode,
@@ -1150,7 +1150,7 @@ void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm)
while (cnt != 0U) {
mg_ucode_img = plsfm->ucode_img_list;
if (mg_ucode_img->ucode_img.lsf_desc->falcon_id ==
LSF_FALCON_ID_PMU) {
FALCON_ID_PMU) {
lsfm_free_ucode_img_res(g, &mg_ucode_img->ucode_img);
} else {
lsfm_free_nonpmu_ucode_img_res(g,
@@ -1243,7 +1243,7 @@ int lsf_gen_wpr_requirements(struct gk20a *g,
/* Finally, update ucode surface size to include updates */
pnode->full_ucode_size = wpr_offset -
pnode->lsb_header.ucode_off;
if (pnode->wpr_header.falcon_id != LSF_FALCON_ID_PMU) {
if (pnode->wpr_header.falcon_id != FALCON_ID_PMU) {
pnode->lsb_header.app_code_off =
pnode->lsb_header.bl_code_size;
pnode->lsb_header.app_code_size =
@@ -1380,7 +1380,7 @@ void nvgpu_gp106_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
acr->g = g;
acr->bootstrap_owner = LSF_FALCON_ID_SEC2;
acr->bootstrap_owner = FALCON_ID_SEC2;
acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
nvgpu_gp106_acr_default_sw_init(g, &acr->acr);

2
drivers/gpu/nvgpu/common/pmu/acr_gv11b.c
View File

@@ -155,7 +155,7 @@ void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
acr->g = g;
acr->bootstrap_owner = LSF_FALCON_ID_PMU;
acr->bootstrap_owner = FALCON_ID_PMU;
acr->max_supported_lsfm = MAX_SUPPORTED_LSFM;
gv11b_acr_default_sw_init(g, &acr->acr);

2
drivers/gpu/nvgpu/common/pmu/acr_tu104.c
View File

@@ -145,7 +145,7 @@ void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
/* Inherit settings from older chip */
nvgpu_gp106_acr_sw_init(g, acr);
acr->bootstrap_owner = LSF_FALCON_ID_GSPLITE;
acr->bootstrap_owner = FALCON_ID_GSPLITE;
acr->max_supported_lsfm = TU104_MAX_SUPPORTED_LSFM;
acr->bootstrap_hs_acr = tu104_bootstrap_hs_acr;
acr->remove_support = tu104_remove_acr_support;

2
drivers/gpu/nvgpu/common/pmu/pmu.c
View File

@@ -312,7 +312,7 @@ int nvgpu_init_pmu_support(struct gk20a *g)
/* Bootstrap PMU from SEC2 RTOS*/
err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2,
LSF_FALCON_ID_PMU);
FALCON_ID_PMU);
if (err != 0) {
goto exit;
}

4
drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c
View File

@@ -230,7 +230,7 @@ int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
unsigned long timeout = gk20a_get_gr_idle_timeout(g);
/* GM20B PMU supports loading FECS only */
if (!(falconidmask == (1 << LSF_FALCON_ID_FECS))) {
if (!(falconidmask == (1 << FALCON_ID_FECS))) {
return -EINVAL;
}
/* check whether pmu is ready to bootstrap lsf if not wait for it */
@@ -247,7 +247,7 @@ int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
/* load FECS */
gk20a_writel(g,
gr_fecs_ctxsw_mailbox_clear_r(0), ~0x0);
gm20b_pmu_load_lsf(g, LSF_FALCON_ID_FECS, flags);
gm20b_pmu_load_lsf(g, FALCON_ID_FECS, flags);
err = pmu_gm20b_ctx_wait_lsf_ready(g, timeout,
0x55AA55AA);
return err;

12
drivers/gpu/nvgpu/common/pmu/pmu_gp106.c
View File

@@ -205,10 +205,10 @@ bool gp106_is_lazy_bootstrap(u32 falcon_id)
bool enable_status = false;
switch (falcon_id) {
case LSF_FALCON_ID_FECS:
case FALCON_ID_FECS:
enable_status = true;
break;
case LSF_FALCON_ID_GPCCS:
case FALCON_ID_GPCCS:
enable_status = true;
break;
default:
@@ -223,10 +223,10 @@ bool gp106_is_priv_load(u32 falcon_id)
bool enable_status = false;
switch (falcon_id) {
case LSF_FALCON_ID_FECS:
case FALCON_ID_FECS:
enable_status = true;
break;
case LSF_FALCON_ID_GPCCS:
case FALCON_ID_GPCCS:
enable_status = true;
break;
default:
@@ -279,8 +279,8 @@ int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
return -EINVAL;
}
if ((falconidmask &
~(BIT32(LSF_FALCON_ID_FECS) |
BIT32(LSF_FALCON_ID_GPCCS))) != 0U) {
~(BIT32(FALCON_ID_FECS) |
BIT32(FALCON_ID_GPCCS))) != 0U) {
return -EINVAL;
}
g->pmu_lsf_loaded_falcon_id = 0;

12
drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c
View File

@@ -182,8 +182,8 @@ int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
return -EINVAL;
}
if ((falconidmask &
~(BIT32(LSF_FALCON_ID_FECS) |
BIT32(LSF_FALCON_ID_GPCCS))) != 0U) {
~(BIT32(FALCON_ID_FECS) |
BIT32(FALCON_ID_GPCCS))) != 0U) {
return -EINVAL;
}
g->pmu_lsf_loaded_falcon_id = 0;
@@ -309,10 +309,10 @@ bool gp10b_is_lazy_bootstrap(u32 falcon_id)
bool enable_status = false;
switch (falcon_id) {
case LSF_FALCON_ID_FECS:
case FALCON_ID_FECS:
enable_status = false;
break;
case LSF_FALCON_ID_GPCCS:
case FALCON_ID_GPCCS:
enable_status = true;
break;
default:
@@ -327,10 +327,10 @@ bool gp10b_is_priv_load(u32 falcon_id)
bool enable_status = false;
switch (falcon_id) {
case LSF_FALCON_ID_FECS:
case FALCON_ID_FECS:
enable_status = false;
break;
case LSF_FALCON_ID_GPCCS:
case FALCON_ID_GPCCS:
enable_status = true;
break;
default:

4
drivers/gpu/nvgpu/common/pmu/pmu_gv100.c
View File

@@ -58,8 +58,8 @@ int gv100_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
}
if ((falconidmask &
~(BIT32(LSF_FALCON_ID_FECS) |
BIT32(LSF_FALCON_ID_GPCCS))) != 0U) {
~(BIT32(FALCON_ID_FECS) |
BIT32(FALCON_ID_GPCCS))) != 0U) {
return -EINVAL;
}

8
drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c
View File

@@ -147,10 +147,10 @@ bool gv11b_is_lazy_bootstrap(u32 falcon_id)
bool enable_status = false;
switch (falcon_id) {
case LSF_FALCON_ID_FECS:
case FALCON_ID_FECS:
enable_status = true;
break;
case LSF_FALCON_ID_GPCCS:
case FALCON_ID_GPCCS:
enable_status = true;
break;
default:
@@ -165,10 +165,10 @@ bool gv11b_is_priv_load(u32 falcon_id)
bool enable_status = false;
switch (falcon_id) {
case LSF_FALCON_ID_FECS:
case FALCON_ID_FECS:
enable_status = false;
break;
case LSF_FALCON_ID_GPCCS:
case FALCON_ID_GPCCS:
enable_status = true;
break;
default:

22
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -792,19 +792,19 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
gr_gm20b_load_gpccs_with_bootloader(g);
err = g->ops.pmu.load_lsfalcon_ucode(g,
(1 << LSF_FALCON_ID_FECS));
(1 << FALCON_ID_FECS));
} else {
/* bind WPR VA inst block */
gr_gk20a_load_falcon_bind_instblk(g);
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) {
err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2,
LSF_FALCON_ID_FECS);
FALCON_ID_FECS);
err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2,
LSF_FALCON_ID_GPCCS);
FALCON_ID_GPCCS);
} else {
err = g->ops.pmu.load_lsfalcon_ucode(g,
(1 << LSF_FALCON_ID_FECS) |
(1 << LSF_FALCON_ID_GPCCS));
(1 << FALCON_ID_FECS) |
(1 << FALCON_ID_GPCCS));
}
}
if (err != 0) {
@@ -820,18 +820,18 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
} else {
/* bind WPR VA inst block */
gr_gk20a_load_falcon_bind_instblk(g);
if (g->ops.pmu.is_lazy_bootstrap(LSF_FALCON_ID_FECS)) {
falcon_id_mask |= BIT8(LSF_FALCON_ID_FECS);
if (g->ops.pmu.is_lazy_bootstrap(FALCON_ID_FECS)) {
falcon_id_mask |= BIT8(FALCON_ID_FECS);
}
if (g->ops.pmu.is_lazy_bootstrap(LSF_FALCON_ID_GPCCS)) {
falcon_id_mask |= BIT8(LSF_FALCON_ID_GPCCS);
if (g->ops.pmu.is_lazy_bootstrap(FALCON_ID_GPCCS)) {
falcon_id_mask |= BIT8(FALCON_ID_GPCCS);
}
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) {
err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2,
LSF_FALCON_ID_FECS);
FALCON_ID_FECS);
err = nvgpu_sec2_bootstrap_ls_falcons(g, &g->sec2,
LSF_FALCON_ID_GPCCS);
FALCON_ID_GPCCS);
} else {
err = g->ops.pmu.load_lsfalcon_ucode(g, falcon_id_mask);
}

18
drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h
View File

@@ -43,18 +43,6 @@
/* Disallow write mis-match for all clients */
#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0U)
/*
* Falcon Id Defines
* Defines a common Light Secure Falcon identifier.
*/
#define LSF_FALCON_ID_PMU 0U
#define LSF_FALCON_ID_GSPLITE 1U
#define LSF_FALCON_ID_FECS 2U
#define LSF_FALCON_ID_GPCCS 3U
#define LSF_FALCON_ID_SEC2 7U
#define LSF_FALCON_ID_END 11U
#define LSF_FALCON_ID_INVALID 0xFFFFFFFFU
/*
* Light Secure Falcon Ucode Description Defines
* This structure is prelim and may change as the ucode signing flow evolves.
@@ -76,7 +64,7 @@ struct lsf_ucode_desc_v1 {
u32 bsupports_versioning;
u32 version;
u32 dep_map_count;
u8 dep_map[LSF_FALCON_ID_END * 2 * 4];
u8 dep_map[FALCON_ID_END * 2 * 4];
u8 kdf[16];
};
@@ -139,7 +127,7 @@ enum {
/*
* Bootstrap Owner Defines
*/
#define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU)
#define LSF_BOOTSTRAP_OWNER_DEFAULT (FALCON_ID_PMU)
/*
* Image Status Defines
@@ -215,7 +203,7 @@ struct lsf_lsb_header_v1 {
* Maximum WPR Header size
*/
#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \
(ALIGN_UP(((u32)sizeof(struct lsf_wpr_header_v1) * LSF_FALCON_ID_END), \
(ALIGN_UP(((u32)sizeof(struct lsf_wpr_header_v1) * FALCON_ID_END), \
LSF_WPR_HEADER_ALIGNMENT))
#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\
ALIGN_UP(sizeof(struct lsf_lsb_header_v1), LSF_LSB_HEADER_ALIGNMENT))

2
drivers/gpu/nvgpu/include/nvgpu/falcon.h
View File

@@ -36,6 +36,8 @@
#define FALCON_ID_NVDEC (4U)
#define FALCON_ID_SEC2 (7U)
#define FALCON_ID_MINION (10U)
#define FALCON_ID_END (11U)
#define FALCON_ID_INVALID 0xFFFFFFFFU
/*
* Falcon Base address Defines

2
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h
View File

@@ -138,7 +138,7 @@ struct nv_pmu_rpc_struct_acr_init_wpr_region {
struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons {
/*[IN/OUT] Must be first field in RPC structure */
struct nv_pmu_rpc_header hdr;
/* [IN] Mask of falcon IDs @ref LSF_FALCON_ID_<XYZ> */
/* [IN] Mask of falcon IDs @ref FALCON_ID_<XYZ> */
u32 falcon_id_mask;
/*
* [IN] Boostrapping flags @ref

2
drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_acr.h
View File

@@ -43,7 +43,7 @@ struct nv_sec2_acr_cmd_bootstrap_falcon {
/* Additional bootstrapping flags */
u32 flags;
/* ID to identify Falcon, ref LSF_FALCON_ID_<XYZ> */
/* ID to identify Falcon, ref FALCON_ID_<XYZ> */
u32 falcon_id;
};