gpu: nvgpu: move fifo RC_TYPE_* definitions to common header

The RC_TYPE_* definitions in fifo_gk20a.h are generic and are moved to
a newly constructed common header <nvgpu/fifo.h>

Jira NVGPU-1237

Change-Id: Ia1bb80b9b0047675c7abfb6ce6ccd42a2e99f41f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970031
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fb/fb_gv11b.c

@@ -33,6 +33,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/timers.h>
+#include <nvgpu/fifo.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -43,6 +43,7 @@
 #include <nvgpu/ptimer.h>
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
+#include <nvgpu/fifo.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/unit.h>

drivers/gpu/nvgpu/gk20a/fifo_gk20a.h

@@ -53,16 +53,6 @@ struct tsg_gk20a;
 
 #define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000U
 
-#define RC_TYPE_NO_RC			0U
-#define RC_TYPE_MMU_FAULT		1U
-#define RC_TYPE_PBDMA_FAULT		2U
-#define RC_TYPE_GR_FAULT		3U
-#define RC_TYPE_PREEMPT_TIMEOUT		4U
-#define RC_TYPE_CTXSW_TIMEOUT		5U
-#define RC_TYPE_RUNLIST_UPDATE_TIMEOUT	6U
-#define RC_TYPE_FORCE_RESET		7U
-#define RC_TYPE_SCHED_ERR		8U
-
 #define NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT	128UL
 #define NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE	3UL
 

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -43,6 +43,7 @@
 #include <nvgpu/ecc.h>
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
+#include <nvgpu/fifo.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/unit.h>

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -40,6 +40,7 @@
 #include <nvgpu/ptimer.h>
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
+#include <nvgpu/fifo.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/unit.h>

drivers/gpu/nvgpu/include/nvgpu/fifo.h

@@ -0,0 +1,38 @@
+/*
+ * fifo common definitions (gr host)
+ *
+ * Copyright (c) 2011-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_FIFO_COMMON_H
+#define NVGPU_FIFO_COMMON_H
+
+#define RC_TYPE_NO_RC			0U
+#define RC_TYPE_MMU_FAULT		1U
+#define RC_TYPE_PBDMA_FAULT		2U
+#define RC_TYPE_GR_FAULT		3U
+#define RC_TYPE_PREEMPT_TIMEOUT		4U
+#define RC_TYPE_CTXSW_TIMEOUT		5U
+#define RC_TYPE_RUNLIST_UPDATE_TIMEOUT	6U
+#define RC_TYPE_FORCE_RESET		7U
+#define RC_TYPE_SCHED_ERR		8U
+
+#endif /* NVGPU_FIFO_COMMON_H */