gpu: nvgpu: Enable sm_l1tag_surface_cut_collector

This is enabling sm_l1tag_surface_cut_collector at gpu boot.
This is done with adding new hal "set_sm_l1tag_surface_collector"
that sets l1tag_surface_cut_collector in the sm_l1tag_ctrl
register.

Bug 2557724

Change-Id: I869e3bfa563db204259e7a464657229632f182d9
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2634878
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile.sources

@@ -781,6 +781,7 @@ srcs += hal/init/hal_ga10b.c \
 	hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c \
 	hal/gr/gr/gr_ga10b.c \
 	hal/gr/init/gr_init_ga10b.c \
+	hal/gr/init/gr_init_ga100.c \
 	hal/gr/init/gr_init_ga10b_fusa.c \
 	hal/gr/intr/gr_intr_ga10b_fusa.c \
 	hal/gr/falcon/gr_falcon_ga10b_fusa.c \
@@ -841,7 +842,6 @@ srcs += \
 	hal/fuse/fuse_ga100.c \
 	hal/gr/intr/gr_intr_ga100_fusa.c \
 	hal/gr/init/gr_init_ga100_fusa.c \
-	hal/gr/init/gr_init_ga100.c \
 	hal/clk/clk_ga100.c \
 	hal/nvdec/nvdec_ga100.c \
 	hal/pmu/pmu_ga100.c \

drivers/gpu/nvgpu/common/gr/gr.c

@@ -21,6 +21,7 @@
  */
 
 #include <nvgpu/gk20a.h>
+#include <nvgpu/errata.h>
 #include <nvgpu/nvgpu_err.h>
 #include <nvgpu/io.h>
 #include <nvgpu/bug.h>
@@ -295,6 +296,11 @@ static int gr_init_setup_hw(struct gk20a *g, struct nvgpu_gr *gr)
 		goto out;
 	}
 
+	if ((nvgpu_is_errata_present(g, NVGPU_ERRATA_2557724)) &&
+		(g->ops.gr.init.set_sm_l1tag_surface_collector != NULL)) {
+			g->ops.gr.init.set_sm_l1tag_surface_collector(g);
+	}
+
 	err = g->ops.gr.init.wait_idle(g);
 out:
 	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, "done");

drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,6 +22,7 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/static_analysis.h>
+#include <nvgpu/io.h>
 
 #include "gr_init_ga100.h"
 
@@ -54,3 +55,11 @@ u32 ga100_gr_init_get_ctx_betacb_size(struct gk20a *g)
 			gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()));
 }
 #endif
+
+void ga100_gr_init_set_sm_l1tag_surface_collector(struct gk20a *g)
+{
+	u32 reg_val = 0U;
+	reg_val = nvgpu_readl(g, gr_gpc0_tpc0_sm_l1tag_ctrl_r());
+	reg_val |= gr_gpcs_tpcs_sm_l1tag_ctrl_surface_cut_collector_enable_f();
+	nvgpu_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), reg_val);
+}

drivers/gpu/nvgpu/hal/gr/init/gr_init_ga100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -36,7 +36,7 @@ u32 ga100_gr_init_get_bundle_cb_token_limit(struct gk20a *g);
 u32 ga100_gr_init_get_attrib_cb_default_size(struct gk20a *g);
 void ga100_gr_init_commit_global_bundle_cb(struct gk20a *g,
 	struct nvgpu_gr_ctx *gr_ctx, u64 addr, u32 size, bool patch);
-
+void ga100_gr_init_set_sm_l1tag_surface_collector(struct gk20a *g);
 #ifdef CONFIG_NVGPU_GRAPHICS
 u32 ga100_gr_init_get_attrib_cb_gfxp_default_size(struct gk20a *g);
 u32 ga100_gr_init_get_attrib_cb_gfxp_size(struct gk20a *g);

drivers/gpu/nvgpu/hal/init/hal_ga100.c

@@ -595,6 +595,7 @@ static const struct gops_gr_init ga100_ops_gr_init = {
 	.gpc_mmu = ga10b_gr_init_gpc_mmu,
 	.reset_gpcs = ga10b_gr_init_reset_gpcs,
 	.fifo_access = gm20b_gr_init_fifo_access,
+	.set_sm_l1tag_surface_collector = ga100_gr_init_set_sm_l1tag_surface_collector,
 #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 	.get_access_map = gv11b_gr_init_get_access_map,
 #endif
@@ -1831,6 +1832,7 @@ int ga100_init_hal(struct gk20a *g)
 	nvgpu_set_errata(g, NVGPU_ERRATA_200601972, true);
 	nvgpu_set_errata(g, NVGPU_ERRATA_200391931, true);
 	nvgpu_set_errata(g, NVGPU_ERRATA_SYNCPT_INVALID_ID_0, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_2557724, true);
 
 	if (gops->fuse.fuse_opt_sm_ttu_en(g) != 0U) {
 		nvgpu_set_enabled(g, NVGPU_SUPPORT_SM_TTU, true);

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -189,6 +189,7 @@
 #include "hal/gr/init/gr_init_gv11b.h"
 #include "hal/gr/init/gr_init_tu104.h"
 #include "hal/gr/init/gr_init_ga10b.h"
+#include "hal/gr/init/gr_init_ga100.h"
 #include "hal/gr/intr/gr_intr_gm20b.h"
 #include "hal/gr/intr/gr_intr_gp10b.h"
 #include "hal/gr/intr/gr_intr_gv11b.h"
@@ -577,6 +578,7 @@ static const struct gops_gr_init ga10b_ops_gr_init = {
 	.eng_config = ga10b_gr_init_eng_config,
 	.reset_gpcs = ga10b_gr_init_reset_gpcs,
 	.fifo_access = gm20b_gr_init_fifo_access,
+	.set_sm_l1tag_surface_collector = ga100_gr_init_set_sm_l1tag_surface_collector,
 #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP
 	.get_access_map = ga10b_gr_init_get_access_map,
 #endif
@@ -1809,6 +1811,7 @@ int ga10b_init_hal(struct gk20a *g)
 	nvgpu_set_errata(g, NVGPU_ERRATA_3154076, true);
 	nvgpu_set_errata(g, NVGPU_ERRATA_3288192, true);
 	nvgpu_set_errata(g, NVGPU_ERRATA_SYNCPT_INVALID_ID_0, true);
+	nvgpu_set_errata(g, NVGPU_ERRATA_2557724, true);
 
 	nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
 

drivers/gpu/nvgpu/include/nvgpu/errata.h

@@ -60,6 +60,7 @@ struct gk20a;
 	DEFINE_ERRATA(NVGPU_ERRATA_VBIOS_NVLINK_MASK, "TU104", "Nvlink VBIOS"),\
 	/* GA100 */							\
 	DEFINE_ERRATA(NVGPU_ERRATA_200601972, "GA100", "LTC TSTG"),     \
+	DEFINE_ERRATA(NVGPU_ERRATA_2557724, "GA100", "L1TAG SURFACE CUT"), \
 	/* GA10B */							\
 	DEFINE_ERRATA(NVGPU_ERRATA_2969956, "GA10B", "FMODEL FB LTCS"),	\
 	DEFINE_ERRATA(NVGPU_ERRATA_200677649, "GA10B", "UCODE"),	\

drivers/gpu/nvgpu/include/nvgpu/gops/gr.h

@@ -900,6 +900,7 @@ struct gops_gr_init {
 	int (*reset_gpcs)(struct gk20a *g);
 	int (*sm_id_config_early)(struct gk20a *g,
 			struct nvgpu_gr_config *config);
+	void (*set_sm_l1tag_surface_collector)(struct gk20a *g);
 	/** @endcond */
 };
 

drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h

@@ -1254,4 +1254,8 @@
 				(((r) >> 0U) & 0x1U)
 #define gr_gpc0_gpccs_engine_reset_ctl_gpc_engine_reset_disabled_v()\
 				(0x00000001U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_r()                             (0x00419bf0U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_surface_cut_collector_enable_f()\
+				(0x20000000U)
+#define gr_gpc0_tpc0_sm_l1tag_ctrl_r()                             (0x005043f0U)
 #endif

drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h

@@ -1214,4 +1214,8 @@
 #define gr_egpcs_etpcs_sm_dsm_perf_counter_control_r()             (0x00481a48U)
 #define gr_egpcs_etpcs_sm_dsm_perf_counter_control0_r()            (0x00481a08U)
 #define gr_egpcs_etpcs_sm_dsm_perf_counter_control5_r()            (0x00481a0cU)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_r()                             (0x00419bf0U)
+#define gr_gpcs_tpcs_sm_l1tag_ctrl_surface_cut_collector_enable_f()\
+				(0x20000000U)
+#define gr_gpc0_tpc0_sm_l1tag_ctrl_r()                             (0x005043f0U)
 #endif