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gpu: nvgpu: configure CWD sm id regs before ucode load

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GPCCS ucode is expecting the SM ID programmed in GPM and CWD registers
to be in sync. So create a hal called gr.init.load_sm_id_config()
for the sm_id programming for the CWD registers and invoke them before
the ucode load.

Initialize this hal only for the required GPUs.

JIRA NVGPU-9757

Change-Id: Ib0984fd6326c37e0c2a06123041032575a23ec04
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864999
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ramalingam C
2023-02-28 18:23:28 +00:00
committed by mobile promotions
parent 3ff15b69de
commit af48120169
4 changed files with 15 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/common/gr/fs_state.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -28,7 +28,7 @@
#include <nvgpu/gr/gr_instances.h> #include <nvgpu/gr/gr_instances.h>
#include <nvgpu/grmgr.h> #include <nvgpu/grmgr.h>
static int gr_load_sm_id_config(struct gk20a *g, struct nvgpu_gr_config *config) int nvgpu_gr_load_sm_id_config(struct gk20a *g, struct nvgpu_gr_config *config)
{ {
int err; int err;
u32 *tpc_sm_id; u32 *tpc_sm_id;
@@ -130,7 +130,7 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
g->ops.gr.init.gr_load_tpc_mask(g, config); g->ops.gr.init.gr_load_tpc_mask(g, config);
} }
err = gr_load_sm_id_config(g, config); err = nvgpu_gr_load_sm_id_config(g, config);
if (err != 0) { if (err != 0) {
nvgpu_err(g, "load_smid_config failed err=%d", err); nvgpu_err(g, "load_smid_config failed err=%d", err);
} }

8
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -818,6 +818,14 @@ static int gr_init_sm_id_config_early(struct gk20a *g, struct nvgpu_gr *gr)
} }
} }
if (g->ops.gr.init.load_sm_id_config != NULL) {
err = g->ops.gr.init.load_sm_id_config(g, gr->config);
if (err != 0) {
nvgpu_err(g, "load_sm_id_config failed err=%d", err);
return err;
}
}
return 0; return 0;
} }

2
drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
View File

@@ -935,6 +935,8 @@ struct gops_gr_init {
int (*reset_gpcs)(struct gk20a *g); int (*reset_gpcs)(struct gk20a *g);
int (*sm_id_config_early)(struct gk20a *g, int (*sm_id_config_early)(struct gk20a *g,
struct nvgpu_gr_config *config); struct nvgpu_gr_config *config);
int (*load_sm_id_config)(struct gk20a *g,
struct nvgpu_gr_config *config);
void (*set_sm_l1tag_surface_collector)(struct gk20a *g); void (*set_sm_l1tag_surface_collector)(struct gk20a *g);
/** @endcond */ /** @endcond */
}; };

3
drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -53,6 +53,7 @@ struct nvgpu_gr_config;
int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config); int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config);
/** @cond DOXYGEN_SHOULD_SKIP_THIS */ /** @cond DOXYGEN_SHOULD_SKIP_THIS */
int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config); int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config);
int nvgpu_gr_load_sm_id_config(struct gk20a *g, struct nvgpu_gr_config *config);
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
#endif /* NVGPU_GR_FS_STATE_H */ #endif /* NVGPU_GR_FS_STATE_H */