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gpu: nvgpu: Update volt pwm source & raw period

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- calculate raw period as per pwm source
- update pwm source for logic & sram rails.

JIRA DNVGPU-123

Change-Id: I50b41d51b6aba760710700522dced7859f815463
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1227626
(cherry picked from commit 6eb5a235dd7bf9031ef1bcfadd6312a2f8758fd4)
Reviewed-on: http://git-master/r/1244663
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2016-09-27 14:54:50 +05:30
committed by Deepak Nibade
parent 741d78ec45
commit af637c81fe
2 changed files with 16 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/gp106/clk_gp106.c
View File

@@ -36,7 +36,12 @@ static int clk_gp106_debugfs_init(struct gk20a *g);
#endif
#define NUM_NAMEMAPS 4
#define XTAL4X_KHZ 108000
static u32 gp106_crystal_clk_hz(struct gk20a *g)
{
return (XTAL4X_KHZ * 1000);
}
static int gp106_init_clk_support(struct gk20a *g) {
struct clk_gk20a *clk = &g->clk;
u32 err = 0;
@@ -221,6 +226,7 @@ err_out:
void gp106_init_clk_ops(struct gpu_ops *gops) {
gops->clk.init_clk_support = gp106_init_clk_support;
gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz;
}

14
drivers/gpu/nvgpu/volt/volt_dev.c
View File

@@ -26,7 +26,6 @@
#include "include/bios.h"
#include "volt.h"
#define RAW_PERIOD 160
#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0
#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1
@@ -257,17 +256,24 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g,
if (ptmp_dev->super.operation_type ==
CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) {
ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1;
if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC)
ptmp_dev->source =
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0;
if (volt_domain == CTRL_VOLT_DOMAIN_SRAM)
ptmp_dev->source =
NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1;
ptmp_dev->raw_period =
g->ops.clk.get_crystal_clk_hz(g) / frequency_hz;
} else if (ptmp_dev->super.operation_type ==
CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) {
ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_0;
ptmp_dev->raw_period = 0;
} else if (ptmp_dev->super.operation_type ==
CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE) {
ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_1;
ptmp_dev->raw_period = 0;
}
ptmp_dev->raw_period = RAW_PERIOD;
/* Initialize data for parent class. */
ptmp_dev->super.super.type = CTRL_VOLT_DEVICE_TYPE_PWM;
ptmp_dev->super.volt_domain = volt_domain;