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gpu: nvgpu: Return gr_ctx_resident from NVGPU_DBG_GPU_IOCTL_REG_OPS

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NVGPU_DBG_GPU_IOCTL_REG_OPS currently doesn't return if the ctx was
resident in engine or not.

Regops are broken down into batches of 128 and each batch is executed
together. Since there only 32 bits were available in IOCTL args, returning
is ctx was resident isn't possible for all batches.
Hence return if the ctx was resident for the first batch.

Bug 200445575

Change-Id: Iff950be25893de0afadd523d4ea04842a8ddf2af
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812975
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Anup Mahindre
2018-09-05 17:36:46 +05:30
committed by mobile promotions
parent e93a4ca50b
commit b026c01296
10 changed files with 32 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -1133,7 +1133,8 @@ struct gpu_ops {
struct {
int (*exec_regops)(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops);
u64 num_ops,
bool *is_current_ctx);
const struct regop_offset_range* (
*get_global_whitelist_ranges)(void);
u64 (*get_global_whitelist_ranges_count)(void);

9
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -8358,7 +8358,8 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops)
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
bool *is_curr_ctx)
{
struct gk20a *g = ch->g;
int err, tmp_err;
@@ -8376,7 +8377,9 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
}
ch_is_curr_ctx = gk20a_is_channel_ctx_resident(ch);
if (is_curr_ctx != NULL) {
*is_curr_ctx = ch_is_curr_ctx;
}
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "is curr ctx=%d",
ch_is_curr_ctx);
@@ -8694,7 +8697,7 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
i++;
}
err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0);
err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0, NULL);
if (err) {
nvgpu_err(g, "Failed to access register");
}

3
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -616,7 +616,8 @@ int gk20a_gr_suspend(struct gk20a *g);
struct nvgpu_dbg_reg_op;
int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops);
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
bool *is_curr_ctx);
int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,

6
drivers/gpu/nvgpu/gk20a/regops_gk20a.c
View File

@@ -89,7 +89,8 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops)
u64 num_ops,
bool *is_current_ctx)
{
int err = 0;
unsigned int i;
@@ -219,7 +220,8 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
if (ctx_wr_count | ctx_rd_count) {
err = gr_gk20a_exec_ctx_ops(ch, ops, num_ops,
ctx_wr_count, ctx_rd_count);
ctx_wr_count, ctx_rd_count,
is_current_ctx);
if (err) {
nvgpu_warn(g, "failed to perform ctx ops\n");
goto clean_up;

5
drivers/gpu/nvgpu/gk20a/regops_gk20a.h
View File

@@ -1,7 +1,7 @@
/*
* Tegra GK20A GPU Debugger Driver Register Ops
*
* Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -77,7 +77,8 @@ struct regop_offset_range {
int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops);
u64 num_ops,
bool *is_current_ctx);
/* turn seriously unwieldy names -> something shorter */
#define REGOP(x) NVGPU_DBG_REG_OP_##x

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -3377,7 +3377,7 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
i++;
}
err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0);
err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0, NULL);
if (err) {
nvgpu_err(g, "Failed to access register\n");
}

9
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
View File

@@ -869,6 +869,9 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
struct gk20a *g = dbg_s->g;
struct channel_gk20a *ch;
bool is_current_ctx;
nvgpu_log_fn(g, "%d ops, max fragment %d", args->num_ops, g->dbg_regops_tmp_buf_ops);
if (args->num_ops > NVGPU_IOCTL_DBG_REG_OPS_LIMIT) {
@@ -954,12 +957,16 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
break;
err = g->ops.regops.exec_regops(
dbg_s, g->dbg_regops_tmp_buf, num_ops);
dbg_s, g->dbg_regops_tmp_buf, num_ops, &is_current_ctx);
if (err) {
break;
}
if (ops_offset == 0) {
args->gr_ctx_resident = is_current_ctx;
}
err = nvgpu_get_regops_data_linux(g->dbg_regops_tmp_buf,
linux_fragment, num_ops);

3
drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
View File

@@ -33,7 +33,8 @@
int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops)
u64 num_ops,
bool *is_current_ctx)
{
struct channel_gk20a *ch;
struct tegra_vgpu_cmd_msg msg;

3
drivers/gpu/nvgpu/vgpu/dbg_vgpu.h
View File

@@ -30,7 +30,8 @@ struct gk20a;
int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_reg_op *ops,
u64 num_ops);
u64 num_ops,
bool *is_current_ctx);
int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate);
bool vgpu_check_and_set_global_reservation(
struct dbg_session_gk20a *dbg_s,

2
include/uapi/linux/nvgpu.h
View File

@@ -1169,7 +1169,7 @@ struct nvgpu_dbg_gpu_reg_op {
struct nvgpu_dbg_gpu_exec_reg_ops_args {
__u64 ops; /* pointer to nvgpu_reg_op operations */
__u32 num_ops;
__u32 _pad0[1];
__u32 gr_ctx_resident;
};
#define NVGPU_DBG_GPU_IOCTL_REG_OPS \