gpu: nvgpu: fix CERT-C errors in hal.fifo.* units

Fix the CERT-C issues of the following type

INT-30-C: Unsigned integer operation "" may wrap.
INT-31-C: Casting "" from "" to "" without checking its value may result
in lost or misinterpreted data.

Jira NVGPU-3881

Change-Id: I1f7e2478f66451f65556f231ee8e32aea8b8ac84
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2170763
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b_fusa.c

@@ -33,7 +33,7 @@
 
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
 
-static const char * const invalid_str = "invalid";
+static const char *invalid_str = "invalid";
 
 static const char *const ctxsw_timeout_status_desc[] = {
 	"awaiting ack",

drivers/gpu/nvgpu/hal/fifo/engines_gp10b_fusa.c

@@ -25,6 +25,7 @@
 #include <nvgpu/log.h>
 #include <nvgpu/errno.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/safe_ops.h>
 
 #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
 
@@ -108,7 +109,7 @@ int gp10b_engine_init_ce_info(struct nvgpu_fifo *f)
 		/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
 		f->active_engines_list[f->num_engines] =
 						dev_info.engine_id;
-		++f->num_engines;
+		f->num_engines = nvgpu_safe_add_u32(f->num_engines, 1U);
 		nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d "
 			"intr_id %d reset_id %d engine_type %d "
 			"engine_enum %d inst_id %d",

drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c

@@ -29,6 +29,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/unit.h>
 #include <nvgpu/power_features/cg.h>
+#include <nvgpu/safe_ops.h>
 
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
 
@@ -94,7 +95,9 @@ u32 gv11b_fifo_mmu_fault_id_to_pbdma_id(struct gk20a *g, u32 mmu_fault_id)
 	fault_id_pbdma0 = fifo_cfg0_pbdma_fault_id_v(reg_val);
 
 	if (mmu_fault_id >= fault_id_pbdma0 &&
-			mmu_fault_id <= fault_id_pbdma0 + num_pbdma - 1U) {
+			mmu_fault_id <= nvgpu_safe_sub_u32(
+					nvgpu_safe_add_u32(fault_id_pbdma0,
+						num_pbdma), 1U)) {
 		return mmu_fault_id - fault_id_pbdma0;
 	}
 

drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b_fusa.c

@@ -33,6 +33,7 @@
 #include <nvgpu/ptimer.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/pbdma_status.h>
+#include <nvgpu/safe_ops.h>
 
 #include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h>
 
@@ -60,11 +61,12 @@ static bool gm20b_pbdma_is_sw_method_subch(struct gk20a *g, u32 pbdma_id,
 	u32 pbdma_method_stride;
 	u32 pbdma_method_reg, pbdma_method_subch;
 
-	pbdma_method_stride = pbdma_method1_r(pbdma_id) -
-				pbdma_method0_r(pbdma_id);
+	pbdma_method_stride = nvgpu_safe_sub_u32(pbdma_method1_r(pbdma_id),
+				pbdma_method0_r(pbdma_id));
 
-	pbdma_method_reg = pbdma_method0_r(pbdma_id) +
-			(pbdma_method_index * pbdma_method_stride);
+	pbdma_method_reg = nvgpu_safe_add_u32(pbdma_method0_r(pbdma_id),
+				nvgpu_safe_mult_u32(pbdma_method_index,
+					pbdma_method_stride));
 
 	pbdma_method_subch = pbdma_method0_subch_v(
 			nvgpu_readl(g, pbdma_method_reg));
@@ -203,11 +205,12 @@ void gm20b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id,
 	u32 pbdma_method_stride;
 	u32 pbdma_method_reg;
 
-	pbdma_method_stride = pbdma_method1_r(pbdma_id) -
-				pbdma_method0_r(pbdma_id);
+	pbdma_method_stride = nvgpu_safe_sub_u32(pbdma_method1_r(pbdma_id),
+				pbdma_method0_r(pbdma_id));
 
-	pbdma_method_reg = pbdma_method0_r(pbdma_id) +
-		(pbdma_method_index * pbdma_method_stride);
+	pbdma_method_reg = nvgpu_safe_add_u32(pbdma_method0_r(pbdma_id),
+				nvgpu_safe_mult_u32(pbdma_method_index,
+					pbdma_method_stride));
 
 	nvgpu_writel(g, pbdma_method_reg,
 			pbdma_method0_valid_true_f() |
@@ -237,7 +240,7 @@ u32 gm20b_pbdma_acquire_val(u64 timeout)
 	BUG_ON(tmp > U64(U32_MAX));
 	val_len = (u32)tmp + 32U;
 	if (val_len == 32U) {
-		val_len = (u32)nvgpu_fls(timeout);
+		val_len = nvgpu_safe_cast_u64_to_u32(nvgpu_fls(timeout));
 	}
 	if (val_len > 16U + pbdma_acquire_timeout_exp_max_v()) { /* man: 16bits */
 		exponent = pbdma_acquire_timeout_exp_max_v();
@@ -410,7 +413,8 @@ u32 gm20b_pbdma_get_gp_base(u64 gpfifo_base)
 u32 gm20b_pbdma_get_gp_base_hi(u64 gpfifo_base, u32 gpfifo_entry)
 {
 	return 	(pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
-		pbdma_gp_base_hi_limit2_f((u32)ilog2(gpfifo_entry)));
+		pbdma_gp_base_hi_limit2_f(
+			nvgpu_safe_cast_u64_to_u32(ilog2(gpfifo_entry))));
 }
 
 u32 gm20b_pbdma_get_fc_subdevice(void)

drivers/gpu/nvgpu/hal/fifo/runlist_ram_gk20a.c

@@ -27,6 +27,7 @@
 #include <nvgpu/engine_status.h>
 #include <nvgpu/engines.h>
 #include <nvgpu/gr/gr_falcon.h>
+#include <nvgpu/safe_ops.h>
 
 #include "runlist_ram_gk20a.h"
 
@@ -53,7 +54,7 @@ void gk20a_runlist_get_tsg_entry(struct nvgpu_tsg *tsg,
 
 	while (timeout > RL_MAX_TIMESLICE_TIMEOUT) {
 		timeout >>= 1U;
-		scale++;
+		scale = nvgpu_safe_add_u32(scale, 1U);
 	}
 
 	if (scale > RL_MAX_TIMESLICE_SCALE) {

drivers/gpu/nvgpu/hal/fifo/runlist_ram_gv11b_fusa.c

@@ -23,6 +23,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/runlist.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/safe_ops.h>
 
 #include "runlist_ram_gv11b.h"
 
@@ -47,7 +48,7 @@ void gv11b_runlist_get_tsg_entry(struct nvgpu_tsg *tsg,
 
 	while (timeout > RL_MAX_TIMESLICE_TIMEOUT) {
 		timeout >>= 1U;
-		scale++;
+		scale = nvgpu_safe_add_u32(scale, 1U);
 	}
 
 	if (scale > RL_MAX_TIMESLICE_SCALE) {

drivers/gpu/nvgpu/hal/fifo/tsg_gv11b_fusa.c

@@ -26,6 +26,7 @@
 #include <nvgpu/tsg.h>
 #include <nvgpu/dma.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/safe_ops.h>
 
 #include "hal/fifo/tsg_gv11b.h"
 
@@ -106,8 +107,9 @@ static u32 gv11b_tsg_get_eng_method_buffer_size(struct gk20a *g)
 	u32 buffer_size;
 	u32 page_size = U32(PAGE_SIZE);
 
-	buffer_size =  ((9U + 1U + 3U) * g->ops.ce.get_num_pce(g)) + 2U;
-	buffer_size = (27U * 5U * buffer_size);
+	buffer_size =  nvgpu_safe_add_u32(nvgpu_safe_mult_u32((9U + 1U + 3U),
+				g->ops.ce.get_num_pce(g)), 2U);
+	buffer_size = nvgpu_safe_mult_u32((27U * 5U), buffer_size);
 	buffer_size = roundup(buffer_size, page_size);
 	nvgpu_log_info(g, "method buffer size in bytes %d", buffer_size);
 

drivers/gpu/nvgpu/hal/fifo/usermode_gv11b_fusa.c

@@ -25,6 +25,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/fifo.h>
+#include <nvgpu/safe_ops.h>
 
 #include "usermode_gv11b.h"
 
@@ -44,7 +45,7 @@ u32 gv11b_usermode_doorbell_token(struct nvgpu_channel *ch)
 {
 	struct gk20a *g = ch->g;
 	struct nvgpu_fifo *f = &g->fifo;
-	u32 hw_chid = f->channel_base + ch->chid;
+	u32 hw_chid = nvgpu_safe_add_u32(f->channel_base, ch->chid);
 
 	return usermode_notify_channel_pending_id_f(hw_chid);
 }