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gpu: nvgpu: gv11b: fifo ops get_mmu_fault_info set to NULL

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mmu fault h/w registers are no longer inside fifo module

JIRA GPUT19X-7
JIRA GPUT19X-12

Change-Id: I7d166f0e80cee7c040289b13a053ff2cdb7d8727
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1487327
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Seema Khowala
2017-05-22 14:53:37 -07:00
committed by mobile promotions
parent 77199c0225
commit b28e43f62b
1 changed files with 1 additions and 0 deletions
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drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
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@@ -1554,6 +1554,7 @@ void gv11b_init_fifo(struct gpu_ops *gops)
gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v;
gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc;
gops->fifo.trigger_mmu_fault = NULL;
gops->fifo.get_mmu_fault_info = NULL;
gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status;
gops->fifo.dump_eng_status = gv11b_dump_eng_status;
gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc;