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gpu: nvgpu: fix MISRA 10.3 issues in hal.ltc

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Change following ltc hal prototype from:
int (*determine_L2_size_bytes)(struct gk20a *gk20a);
to
u64 (*determine_L2_size_bytes)(struct gk20a *gk20a);

JIRA NVGPU-3422

Change-Id: I53cbd7f37cad3c6851e3c5b46af6cdc04013d690
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119996
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-05-15 22:03:29 -07:00
committed by mobile promotions
parent 80adcd99e8
commit b2980b0c22
7 changed files with 15 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/vgpu/ltc/ltc_vgpu.c
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@@ -27,7 +27,7 @@
#include "ltc_vgpu.h"
int vgpu_determine_L2_size_bytes(struct gk20a *g)
u64 vgpu_determine_L2_size_bytes(struct gk20a *g)
{
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);

2
drivers/gpu/nvgpu/common/vgpu/ltc/ltc_vgpu.h
View File

@@ -26,7 +26,7 @@
struct gk20a;
struct gr_gk20a;
int vgpu_determine_L2_size_bytes(struct gk20a *g);
u64 vgpu_determine_L2_size_bytes(struct gk20a *g);
void vgpu_ltc_init_fs_state(struct gk20a *g);
#endif /* NVGPU_LTC_VGPU_H */

9
drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.c
View File

@@ -162,20 +162,20 @@ void gm20b_flush_ltc(struct gk20a *g)
}
}
int gm20b_determine_L2_size_bytes(struct gk20a *g)
u64 gm20b_determine_L2_size_bytes(struct gk20a *g)
{
u32 lts_per_ltc;
u32 ways;
u32 sets;
u32 bytes_per_line;
u32 active_ltcs;
u32 cache_size;
u64 cache_size;
u32 tmp;
u32 active_sets_value;
tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_cfg1_r());
ways = hweight32(ltc_ltc0_lts0_tstg_cfg1_active_ways_v(tmp));
ways = (u32)hweight32(ltc_ltc0_lts0_tstg_cfg1_active_ways_v(tmp));
active_sets_value = ltc_ltc0_lts0_tstg_cfg1_active_sets_v(tmp);
if (active_sets_value == ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v()) {
@@ -197,7 +197,8 @@ int gm20b_determine_L2_size_bytes(struct gk20a *g)
/* chip-specific values */
lts_per_ltc = 2U;
bytes_per_line = 128U;
cache_size = active_ltcs * lts_per_ltc * ways * sets * bytes_per_line;
cache_size = active_ltcs * (u64)lts_per_ltc * ways *
(u64) sets * bytes_per_line;
return cache_size;
}

2
drivers/gpu/nvgpu/hal/ltc/ltc_gm20b.h
View File

@@ -30,7 +30,7 @@
struct gk20a;
struct gr_gk20a;
int gm20b_determine_L2_size_bytes(struct gk20a *g);
u64 gm20b_determine_L2_size_bytes(struct gk20a *g);
void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
u32 *color_l2,
u32 index);

10
drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.c
View File

@@ -32,20 +32,20 @@
#include "ltc_gm20b.h"
#include "ltc_gp10b.h"
int gp10b_determine_L2_size_bytes(struct gk20a *g)
u64 gp10b_determine_L2_size_bytes(struct gk20a *g)
{
u32 tmp;
int ret;
u64 ret;
nvgpu_log_fn(g, " ");
tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r());
ret = g->ltc->ltc_count *
ret = (u64)g->ltc->ltc_count *
ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp) * 1024U *
ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp);
(u64)ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp);
nvgpu_log(g, gpu_dbg_info, "L2 size: %d\n", ret);
nvgpu_log(g, gpu_dbg_info, "L2 size: %llu\n", ret);
nvgpu_log_fn(g, "done");

2
drivers/gpu/nvgpu/hal/ltc/ltc_gp10b.h
View File

@@ -24,7 +24,7 @@
#define LTC_GP10B_H
struct gk20a;
int gp10b_determine_L2_size_bytes(struct gk20a *g);
u64 gp10b_determine_L2_size_bytes(struct gk20a *g);
void gp10b_ltc_init_fs_state(struct gk20a *g);
void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled);
#endif

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -209,7 +209,7 @@ enum nvgpu_event_id_type {
struct gpu_ops {
struct {
int (*determine_L2_size_bytes)(struct gk20a *gk20a);
u64 (*determine_L2_size_bytes)(struct gk20a *gk20a);
void (*set_zbc_color_entry)(struct gk20a *g,
u32 *color_val_l2,
u32 index);