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gpu: nvgpu: Fix MISRA 15.7 violation in priv_ring

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MISRA 15.7 does not allow empty terminating "else" statement.
Add INFO level print in the else condition to conform to
MISRA 15.7.

JIRA NVGPU-1490

Change-Id: If4da58f874cf84ccce20e01075e05a1d1ade37fc
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1967591
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
tkudav
2018-12-07 15:06:33 +05:30
committed by mobile promotions
parent ba85fc999b
commit b361c38bca
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c
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@@ -96,6 +96,9 @@ void gp10b_priv_ring_decode_error_code(struct gk20a *g,
nvgpu_err(g, "%s",
error_type_badf5xyy[error_type_index]);
}
} else {
nvgpu_log_info(g, "Decoding error code 0x%x not supported.",
error_code);
}
}