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gpu: nvgpu: Re-factor BIOS unit

Browse Source 
- Create nvlink_bios.c/.h files to separate out nvlink
  related bios code.
- Create bios_sw_<chip speciific>.c/.h files to separate
  out chips specific bios code.
- Create hal files for bios under hal/bios/ and move
  hardware specific code there.
- Move hardware accessing hal files from common/top
  to hal/top

JIRA NVGPU-2071

Change-Id: Ia466f1cd8947540b07b237e891312123df2c6b46
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107371
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2019-04-12 09:29:19 +05:30
committed by mobile promotions
parent 8f24fc351e
commit b368dc48b3
39 changed files with 694 additions and 473 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/nvgpu/Makefile
View File

@@ -38,10 +38,6 @@ nvgpu-y += \
common/perf/perfbuf.o \
common/xve/xve_gp106.o \
common/therm/therm.o \
common/top/top_gm20b.o \
common/top/top_gp10b.o \
common/top/top_gv100.o \
common/top/top_gv11b.o \
common/mc/mc.o \
common/worker.o \
common/sync/channel_sync.o \
@@ -325,7 +321,14 @@ nvgpu-y += \
hal/pmu/pmu_gp10b.o \
hal/pmu/pmu_gp106.o \
hal/pmu/pmu_gv11b.o \
hal/pmu/pmu_tu104.o
hal/pmu/pmu_tu104.o \
hal/bios/bios_tu104.o \
hal/top/top_gm20b.o \
hal/top/top_gp10b.o \
hal/top/top_gp106.o \
hal/top/top_gv100.o \
hal/top/top_gv11b.o \
# Linux specific parts of nvgpu.
nvgpu-y += \
@@ -484,6 +487,10 @@ nvgpu-y += \
common/pramin.o \
common/rbtree.o \
common/vbios/bios.o \
common/vbios/nvlink_bios.o \
common/vbios/bios_sw_gp106.o \
common/vbios/bios_sw_gv100.o \
common/vbios/bios_sw_tu104.o \
common/falcon/falcon.o \
common/falcon/falcon_sw_gk20a.o \
common/falcon/falcon_sw_gp106.o \
@@ -575,10 +582,7 @@ nvgpu-$(CONFIG_GK20A_CYCLE_STATS) += \
nvgpu-y += \
gp10b/mm_gp10b.o \
gp106/bios_gp106.o \
gv11b/mm_gv11b.o \
gv100/mm_gv100.o \
gv100/bios_gv100.o \
tu104/mm_tu104.o \
tu104/fifo_tu104.o \
tu104/bios_tu104.o

19
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -83,10 +83,6 @@ srcs += common/sim/sim.c \
common/perf/perfbuf.c \
common/perf/cyclestats_snapshot.c \
common/cyclestats/cyclestats.c \
common/top/top_gm20b.c \
common/top/top_gp10b.c \
common/top/top_gv100.c \
common/top/top_gv11b.c \
common/enabled.c \
common/pramin.c \
common/string.c \
@@ -97,6 +93,10 @@ srcs += common/sim/sim.c \
common/ecc.c \
common/ce/ce.c \
common/vbios/bios.c \
common/vbios/nvlink_bios.c \
common/vbios/bios_sw_gp106.c \
common/vbios/bios_sw_gv100.c \
common/vbios/bios_sw_tu104.c \
common/falcon/falcon.c \
common/falcon/falcon_sw_gk20a.c \
common/falcon/falcon_sw_gp106.c \
@@ -247,10 +247,7 @@ srcs += common/sim/sim.c \
gm20b/mm_gm20b.c \
gp10b/mm_gp10b.c \
gv11b/mm_gv11b.c \
gp106/bios_gp106.c \
gv100/mm_gv100.c \
gv100/bios_gv100.c \
tu104/bios_tu104.c \
tu104/fifo_tu104.c \
tu104/mm_tu104.c \
hal/mm/cache/flush_gk20a.c \
@@ -428,7 +425,13 @@ srcs += common/sim/sim.c \
hal/pmu/pmu_gp10b.c \
hal/pmu/pmu_gp106.c \
hal/pmu/pmu_gv11b.c \
hal/pmu/pmu_tu104.c
hal/pmu/pmu_tu104.c \
hal/bios/bios_tu104.c \
hal/top/top_gm20b.c \
hal/top/top_gp10b.c \
hal/top/top_gp106.c \
hal/top/top_gv100.c \
hal/top/top_gv11b.c
ifeq ($(NVGPU_DEBUGGER),1)
srcs += common/debugger.c

2
drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c
View File

@@ -23,7 +23,7 @@
#ifdef CONFIG_TEGRA_NVLINK
#include <nvgpu/nvgpu_common.h>
#include <nvgpu/bios.h>
#include <nvgpu/nvlink_bios.h>
#include <nvgpu/bitops.h>
#include <nvgpu/nvlink.h>
#include <nvgpu/enabled.h>

2
drivers/gpu/nvgpu/common/nvlink/nvlink_tu104.c
View File

@@ -29,7 +29,7 @@
#include <nvgpu/io.h>
#include <nvgpu/timers.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/bios.h>
#include <nvgpu/nvlink_bios.h>
#include <nvgpu/nvlink_minion.h>
#include "nvlink_gv100.h"

2
drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c
View File

@@ -29,7 +29,7 @@
#include <nvgpu/pmu/cmd.h>
#include <nvgpu/pmu/pmu_pstate.h>
#include "gp106/bios_gp106.h"
#include "common/vbios/bios_sw_gp106.h"
#include "lpwr.h"
static int get_lpwr_idx_table(struct gk20a *g)

2
drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/pmu/cmd.h>
#include <nvgpu/pmu/pmu_pstate.h>
#include "gp106/bios_gp106.h"
#include "common/vbios/bios_sw_gp106.h"
static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
void *param, u32 status)

2
drivers/gpu/nvgpu/common/pmu/pmgr/pmgrpmu.c
View File

@@ -30,7 +30,7 @@
#include <nvgpu/bug.h>
#include <nvgpu/pmu/cmd.h>
#include "gp106/bios_gp106.h"
#include "common/vbios/bios_sw_gp106.h"
#include "pwrdev.h"
#include "pmgr.h"

2
drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c
View File

@@ -28,7 +28,7 @@
#include "pwrdev.h"
#include "pmgr.h"
#include "gp106/bios_gp106.h"
#include "common/vbios/bios_sw_gp106.h"
static int _pwr_device_pmudata_instget(struct gk20a *g,
struct nv_pmu_boardobjgrp *pmuboardobjgrp,

2
drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c
View File

@@ -28,7 +28,7 @@
#include "pwrdev.h"
#include "pmgr.h"
#include "gp106/bios_gp106.h"
#include "common/vbios/bios_sw_gp106.h"
static int _pwr_channel_pmudata_instget(struct gk20a *g,
struct nv_pmu_boardobjgrp *pmuboardobjgrp,

2
drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c
View File

@@ -29,7 +29,7 @@
#include "pwrpolicy.h"
#include "pmgr.h"
#include "gp106/bios_gp106.h"
#include "common/vbios/bios_sw_gp106.h"
#define _pwr_policy_limitarboutputget_helper(p_limit_arb) (p_limit_arb)->output
#define _pwr_policy_limitdeltaapply(limit, delta) ((u32)max(((s32)limit) + (delta), 0))

338
drivers/gpu/nvgpu/common/vbios/bios.c
View File

@@ -25,25 +25,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/string.h>
#define BIT_HEADER_ID 0xb8ffU
#define BIT_HEADER_SIGNATURE 0x00544942U
#define PCI_EXP_ROM_SIG 0xaa55U
#define PCI_EXP_ROM_SIG_NV 0x4e56U
#define INIT_DONE 0x71U
#define INIT_RESUME 0x72U
#define INIT_CONDITION 0x75U
#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8fU
#define PCI_ROM_IMAGE_BLOCK_SIZE 512U
#define PCI_DATA_STRUCTURE_CODE_TYPE_VBIOS_BASE 0x00U
#define PCI_DATA_STRUCTURE_CODE_TYPE_VBIOS_UEFI 0x03U
struct condition_entry {
u32 cond_addr;
u32 cond_mask;
u32 cond_compare;
} __packed;
static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset);
static u16 nvgpu_bios_rdu16(struct gk20a *g, u32 offset)
{
@@ -61,245 +43,6 @@ static u32 nvgpu_bios_rdu32(struct gk20a *g, u32 offset)
return val;
}
struct bios_bit {
u16 id;
u32 signature;
u16 bcd_version;
u8 header_size;
u8 token_size;
u8 token_entries;
u8 header_checksum;
} __packed;
#define TOKEN_ID_BIOSDATA 0x42U
#define TOKEN_ID_NVINIT_PTRS 0x49U
#define TOKEN_ID_FALCON_DATA 0x70U
#define TOKEN_ID_PERF_PTRS 0x50U
#define TOKEN_ID_CLOCK_PTRS 0x43U
#define TOKEN_ID_VIRT_PTRS 0x56U
#define TOKEN_ID_MEMORY_PTRS 0x4DU
#define NVLINK_CONFIG_DATA_HDR_VER_10 0x1U
#define NVLINK_CONFIG_DATA_HDR_10_SIZE 16U
#define NVLINK_CONFIG_DATA_HDR_11_SIZE 17U
#define NVLINK_CONFIG_DATA_HDR_12_SIZE 21U
struct nvlink_config_data_hdr_v1 {
u8 version;
u8 hdr_size;
u16 rsvd0;
u32 link_disable_mask;
u32 link_mode_mask;
u32 link_refclk_mask;
u8 train_at_boot;
u32 ac_coupling_mask;
} __packed;
#define LWPR_NVLINK_TABLE_10_HDR_VER_10 0x10U
#define LPWR_NVLINK_TABLE_10_HDR_SIZE_06 6U
struct lpwr_nvlink_table_hdr_v1 {
u8 version;
u8 hdr_size;
u8 entry_size;
u8 entry_count;
u8 default_entry_idx;
u8 line_rate_initpll_ordinal;
} __packed;
#define MEMORY_PTRS_V1 1U
#define MEMORY_PTRS_V2 2U
struct memory_ptrs_v1 {
u8 rsvd0[2];
u8 mem_strap_data_count;
u16 mem_strap_xlat_tbl_ptr;
u8 rsvd1[8];
} __packed;
struct memory_ptrs_v2 {
u8 mem_strap_data_count;
u16 mem_strap_xlat_tbl_ptr;
u8 rsvd[14];
} __packed;
struct biosdata {
u32 version;
u8 oem_version;
u8 checksum;
u16 int15callbackspost;
u16 int16callbackssystem;
u16 boardid;
u16 framecount;
u8 biosmoddate[8];
} __packed;
struct nvinit_ptrs {
u16 initscript_table_ptr;
u16 macro_index_table_ptr;
u16 macro_table_ptr;
u16 condition_table_ptr;
u16 io_condition_table_ptr;
u16 io_flag_condition_table_ptr;
u16 init_function_table_ptr;
u16 vbios_private_table_ptr;
u16 data_arrays_table_ptr;
u16 pcie_settings_script_ptr;
u16 devinit_tables_ptr;
u16 devinit_tables_size;
u16 bootscripts_ptr;
u16 bootscripts_size;
u16 nvlink_config_data_ptr;
} __packed;
struct falcon_data_v2 {
u32 falcon_ucode_table_ptr;
} __packed;
struct falcon_ucode_table_hdr_v1 {
u8 version;
u8 header_size;
u8 entry_size;
u8 entry_count;
u8 desc_version;
u8 desc_size;
} __packed;
struct falcon_ucode_table_entry_v1 {
u8 application_id;
u8 target_id;
u32 desc_ptr;
} __packed;
#define TARGET_ID_PMU 0x01U
#define APPLICATION_ID_DEVINIT 0x04U
#define APPLICATION_ID_PRE_OS 0x01U
#define FALCON_UCODE_FLAGS_VERSION_AVAILABLE 0x1U
#define FALCON_UCODE_IS_VERSION_AVAILABLE(hdr) \
(((hdr).v2.v_desc & FALCON_UCODE_FLAGS_VERSION_AVAILABLE) == \
FALCON_UCODE_FLAGS_VERSION_AVAILABLE)
/*
* version is embedded in bits 8:15 of the header on version 2+
* and the header length in bits 16:31
*/
#define FALCON_UCODE_GET_VERSION(hdr) \
U8(((hdr).v2.v_desc >> 8) & 0xffU)
#define FALCON_UCODE_GET_DESC_SIZE(hdr) \
U16(((hdr).v2.v_desc >> 16) & 0xffffU)
struct falcon_ucode_desc_v1 {
union {
u32 v_desc;
u32 stored_size;
} hdr_size;
u32 uncompressed_size;
u32 virtual_entry;
u32 interface_offset;
u32 imem_phys_base;
u32 imem_load_size;
u32 imem_virt_base;
u32 imem_sec_base;
u32 imem_sec_size;
u32 dmem_offset;
u32 dmem_phys_base;
u32 dmem_load_size;
} __packed;
struct falcon_ucode_desc_v2 {
u32 v_desc;
u32 stored_size;
u32 uncompressed_size;
u32 virtual_entry;
u32 interface_offset;
u32 imem_phys_base;
u32 imem_load_size;
u32 imem_virt_base;
u32 imem_sec_base;
u32 imem_sec_size;
u32 dmem_offset;
u32 dmem_phys_base;
u32 dmem_load_size;
u32 alt_imem_load_size;
u32 alt_dmem_load_size;
} __packed;
union falcon_ucode_desc {
struct falcon_ucode_desc_v1 v1;
struct falcon_ucode_desc_v2 v2;
};
struct application_interface_table_hdr_v1 {
u8 version;
u8 header_size;
u8 entry_size;
u8 entry_count;
} __packed;
struct application_interface_entry_v1 {
u32 id;
u32 dmem_offset;
} __packed;
#define APPINFO_ID_DEVINIT 0x01U
struct devinit_engine_interface {
u16 version;
u16 size;
u16 application_version;
u16 application_features;
u32 tables_phys_base;
u32 tables_virt_base;
u32 script_phys_base;
u32 script_virt_base;
u32 script_virt_entry;
u16 script_size;
u8 memory_strap_count;
u8 reserved;
u32 memory_information_table_virt_base;
u32 empty_script_virt_base;
u32 cond_table_virt_base;
u32 io_cond_table_virt_base;
u32 data_arrays_table_virt_base;
u32 gpio_assignment_table_virt_base;
} __packed;
struct pci_exp_rom {
u16 sig;
u8 reserved[0x16];
u16 pci_data_struct_ptr;
u32 size_of_block;
} __packed;
struct pci_data_struct {
u32 sig;
u16 vendor_id;
u16 device_id;
u16 device_list_ptr;
u16 pci_data_struct_len;
u8 pci_data_struct_rev;
u8 class_code[3];
u16 image_len;
u16 vendor_rom_rev;
u8 code_type;
u8 last_image;
u16 max_runtime_image_len;
} __packed;
struct pci_ext_data_struct {
u32 sig;
u16 nv_pci_data_ext_rev;
u16 nv_pci_data_ext_len;
u16 sub_image_len;
u8 priv_last_image;
u8 flags;
} __packed;
static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset);
int nvgpu_bios_parse_rom(struct gk20a *g)
{
u32 offset = 0;
@@ -429,85 +172,6 @@ static void nvgpu_bios_parse_nvinit_ptrs(struct gk20a *g, u32 offset)
g->bios.condition_table_ptr = nvinit_ptrs.condition_table_ptr;
g->bios.nvlink_config_data_offset = nvinit_ptrs.nvlink_config_data_ptr;
}
int nvgpu_bios_get_nvlink_config_data(struct gk20a *g)
{
int ret = 0;
struct nvlink_config_data_hdr_v1 config;
if (g->bios.nvlink_config_data_offset == 0U) {
return -EINVAL;
}
nvgpu_memcpy((u8 *)&config,
&g->bios.data[g->bios.nvlink_config_data_offset],
sizeof(config));
if (config.version != NVLINK_CONFIG_DATA_HDR_VER_10) {
nvgpu_err(g, "unsupported nvlink bios version: 0x%x",
config.version);
return -EINVAL;
}
switch (config.hdr_size) {
case NVLINK_CONFIG_DATA_HDR_12_SIZE:
g->nvlink.ac_coupling_mask = config.ac_coupling_mask;
g->nvlink.train_at_boot = config.train_at_boot;
g->nvlink.link_disable_mask = config.link_disable_mask;
g->nvlink.link_mode_mask = config.link_mode_mask;
g->nvlink.link_refclk_mask = config.link_refclk_mask;
break;
case NVLINK_CONFIG_DATA_HDR_11_SIZE:
g->nvlink.train_at_boot = config.train_at_boot;
g->nvlink.link_disable_mask = config.link_disable_mask;
g->nvlink.link_mode_mask = config.link_mode_mask;
g->nvlink.link_refclk_mask = config.link_refclk_mask;
break;
case NVLINK_CONFIG_DATA_HDR_10_SIZE:
g->nvlink.link_disable_mask = config.link_disable_mask;
g->nvlink.link_mode_mask = config.link_mode_mask;
g->nvlink.link_refclk_mask = config.link_refclk_mask;
break;
default:
nvgpu_err(g, "invalid nvlink bios config size");
ret = -EINVAL;
break;
}
return ret;
}
int nvgpu_bios_get_lpwr_nvlink_table_hdr(struct gk20a *g)
{
struct lpwr_nvlink_table_hdr_v1 hdr;
u8 *lpwr_nvlink_tbl_hdr_ptr = NULL;
lpwr_nvlink_tbl_hdr_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token,
LPWR_NVLINK_TABLE);
if (lpwr_nvlink_tbl_hdr_ptr == NULL) {
nvgpu_err(g, "Invalid pointer to LPWR_NVLINK_TABLE\n");
return -EINVAL;
}
nvgpu_memcpy((u8 *)&hdr, lpwr_nvlink_tbl_hdr_ptr,
LPWR_NVLINK_TABLE_10_HDR_SIZE_06);
if (hdr.version != LWPR_NVLINK_TABLE_10_HDR_VER_10) {
nvgpu_err(g, "Unsupported LPWR_NVLINK_TABLE version: 0x%x",
hdr.version);
return -EINVAL;
}
g->nvlink.initpll_ordinal =
BIOS_GET_FIELD(u8, hdr.line_rate_initpll_ordinal,
VBIOS_LPWR_NVLINK_TABLE_HDR_INITPLL_ORDINAL);
nvgpu_log(g, gpu_dbg_nvlink, " Nvlink initpll_ordinal: 0x%x",
g->nvlink.initpll_ordinal);
return 0;
}
static void nvgpu_bios_parse_memory_ptrs(struct gk20a *g, u16 offset, u8 version)
{
struct memory_ptrs_v1 v1;

111
drivers/gpu/nvgpu/gp106/bios_gp106.c → drivers/gpu/nvgpu/common/vbios/bios_sw_gp106.c
View File

@@ -29,10 +29,9 @@
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include "bios_gp106.h"
#include "hal/top/top_gp106.h"
#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
#include <nvgpu/hw/gp106/hw_top_gp106.h>
#include "bios_sw_gp106.h"
#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */
#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */
@@ -41,42 +40,12 @@
#define ROM_FILE_PAYLOAD_OFFSET 0xa00
#define BIOS_SIZE 0x90000
static void upload_code(struct gk20a *g, u32 dst,
u8 *src, u32 size, u8 port, bool sec)
{
nvgpu_falcon_copy_to_imem(&g->pmu.flcn, dst, src, size, port, sec,
dst >> 8);
}
static void upload_data(struct gk20a *g, u32 dst, u8 *src, u32 size, u8 port)
{
u32 i, words;
u32 *src_u32 = (u32 *)src;
u32 blk;
nvgpu_log_info(g, "upload %d bytes to %x", size, dst);
words = DIV_ROUND_UP(size, 4U);
blk = dst >> 8;
nvgpu_log_info(g, "upload %d words to %x blk %d",
words, dst, blk);
gk20a_writel(g, pwr_falcon_dmemc_r(port),
pwr_falcon_dmemc_offs_f(dst >> 2) |
pwr_falcon_dmemc_blk_f(blk) |
pwr_falcon_dmemc_aincw_f(1));
for (i = 0; i < words; i++) {
gk20a_writel(g, pwr_falcon_dmemd_r(port), src_u32[i]);
}
}
int gp106_bios_devinit(struct gk20a *g)
{
int err = 0;
bool devinit_completed;
struct nvgpu_timeout timeout;
u32 top_scratch1_reg;
nvgpu_log_fn(g, " ");
@@ -85,26 +54,51 @@ int gp106_bios_devinit(struct gk20a *g)
goto out;
}
upload_code(g, g->bios.devinit.bootloader_phys_base,
err = nvgpu_falcon_copy_to_imem(&g->pmu.flcn,
g->bios.devinit.bootloader_phys_base,
g->bios.devinit.bootloader,
g->bios.devinit.bootloader_size,
0, 0);
upload_code(g, g->bios.devinit.phys_base,
0, 0, g->bios.devinit.bootloader_phys_base >> 8);
if (err != 0) {
nvgpu_err(g, "bios devinit bootloader copy failed %d", err);
goto out;
}
err = nvgpu_falcon_copy_to_imem(&g->pmu.flcn, g->bios.devinit.phys_base,
g->bios.devinit.ucode,
g->bios.devinit.size,
0, 1);
upload_data(g, g->bios.devinit.dmem_phys_base,
0, 1, g->bios.devinit.phys_base >> 8);
if (err != 0) {
nvgpu_err(g, "bios devinit ucode copy failed %d", err);
goto out;
}
err = nvgpu_falcon_copy_to_dmem(&g->pmu.flcn, g->bios.devinit.dmem_phys_base,
g->bios.devinit.dmem,
g->bios.devinit.dmem_size,
0);
upload_data(g, g->bios.devinit_tables_phys_base,
if (err != 0) {
nvgpu_err(g, "bios devinit dmem copy failed %d", err);
goto out;
}
err = nvgpu_falcon_copy_to_dmem(&g->pmu.flcn, g->bios.devinit_tables_phys_base,
g->bios.devinit_tables,
g->bios.devinit_tables_size,
0);
upload_data(g, g->bios.devinit_script_phys_base,
if (err != 0) {
nvgpu_err(g, "fbios devinit tables copy failed %d", err);
goto out;
}
err = nvgpu_falcon_copy_to_dmem(&g->pmu.flcn, g->bios.devinit_script_phys_base,
g->bios.bootscripts,
g->bios.bootscripts_size,
0);
if (err != 0) {
nvgpu_err(g, "bios devinit bootscripts copy failed %d", err);
goto out;
}
err = nvgpu_falcon_bootstrap(&g->pmu.flcn,
g->bios.devinit.code_entry_point);
@@ -118,10 +112,12 @@ int gp106_bios_devinit(struct gk20a *g)
PMU_BOOT_TIMEOUT_DEFAULT,
NVGPU_TIMER_RETRY_TIMER);
do {
devinit_completed = (pwr_falcon_cpuctl_halt_intr_v(
gk20a_readl(g, pwr_falcon_cpuctl_r())) != 0U) &&
(top_scratch1_devinit_completed_v(
gk20a_readl(g, top_scratch1_r())) != 0U);
top_scratch1_reg = g->ops.top.read_top_scratch1_reg(g);
devinit_completed = ((g->ops.falcon.is_falcon_cpu_halted(
&g->pmu.flcn) != 0U) &&
(g->ops.top.top_scratch1_devinit_completed(g,
top_scratch1_reg)) != 0U);
nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
} while (!devinit_completed && (nvgpu_timeout_expired(&timeout) == 0));
@@ -163,18 +159,33 @@ int gp106_bios_preos(struct gk20a *g)
g->ops.bios.preos_reload_check(g);
}
upload_code(g, g->bios.preos.bootloader_phys_base,
err = nvgpu_falcon_copy_to_imem(&g->pmu.flcn,
g->bios.preos.bootloader_phys_base,
g->bios.preos.bootloader,
g->bios.preos.bootloader_size,
0, 0);
upload_code(g, g->bios.preos.phys_base,
0, 0, g->bios.preos.bootloader_phys_base >> 8);
if (err != 0) {
nvgpu_err(g, "bios preos bootloader copy failed %d", err);
goto out;
}
err = nvgpu_falcon_copy_to_imem(&g->pmu.flcn, g->bios.preos.phys_base,
g->bios.preos.ucode,
g->bios.preos.size,
0, 1);
upload_data(g, g->bios.preos.dmem_phys_base,
0, 1, g->bios.preos.phys_base >> 8);
if (err != 0) {
nvgpu_err(g, "bios preos ucode copy failed %d", err);
goto out;
}
err = nvgpu_falcon_copy_to_dmem(&g->pmu.flcn, g->bios.preos.dmem_phys_base,
g->bios.preos.dmem,
g->bios.preos.dmem_size,
0);
if (err != 0) {
nvgpu_err(g, "bios preos dmem copy failed %d", err);
goto out;
}
err = nvgpu_falcon_bootstrap(&g->pmu.flcn,
g->bios.preos.code_entry_point);

10
drivers/gpu/nvgpu/gp106/bios_gp106.h → drivers/gpu/nvgpu/common/vbios/bios_sw_gp106.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,14 +20,14 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_BIOS_GP106_H
#define NVGPU_BIOS_GP106_H
#ifndef NVGPU_BIOS_SW_GP106_H
#define NVGPU_BIOS_SW_GP106_H
struct gk20a;
struct gpu_ops;
int gp106_bios_init(struct gk20a *g);
int gp106_bios_preos_wait_for_halt(struct gk20a *g);
int gp106_bios_devinit(struct gk20a *g);
int gp106_bios_preos(struct gk20a *g);
#endif
#endif /* NVGPU_BIOS_SW_GP106_H */

16
drivers/gpu/nvgpu/gv100/bios_gv100.c → drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -26,10 +26,8 @@
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include "gp106/bios_gp106.h"
#include "bios_gv100.h"
#include <nvgpu/hw/gv100/hw_pwr_gv100.h>
#include "bios_sw_gp106.h"
#include "bios_sw_gv100.h"
#define PMU_BOOT_TIMEOUT_DEFAULT 100U /* usec */
#define PMU_BOOT_TIMEOUT_MAX 2000000U /* usec */
@@ -92,11 +90,13 @@ int gv100_bios_preos_wait_for_halt(struct gk20a *g)
NVGPU_TIMER_RETRY_TIMER);
do {
progress = g->ops.bus.read_sw_scratch(g, SCRATCH_PREOS_PROGRESS);
preos_completed = (pwr_falcon_cpuctl_halt_intr_v(
gk20a_readl(g, pwr_falcon_cpuctl_r())) != 0U) &&
progress = g->ops.bus.read_sw_scratch(g,
SCRATCH_PREOS_PROGRESS);
preos_completed = (g->ops.falcon.is_falcon_cpu_halted(
&g->pmu.flcn) != 0U) &&
(PREOS_PROGRESS_MASK(progress) ==
PREOS_PROGRESS_EXIT);
nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
} while (!preos_completed &&
(nvgpu_timeout_expired(&timeout) == 0));

8
drivers/gpu/nvgpu/gv100/bios_gv100.h → drivers/gpu/nvgpu/common/vbios/bios_sw_gv100.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,12 +20,12 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_BIOS_GV100_H
#define NVGPU_BIOS_GV100_H
#ifndef NVGPU_BIOS_SW_GV100_H
#define NVGPU_BIOS_SW_GV100_H
struct gk20a;
void gv100_bios_preos_reload_check(struct gk20a *g);
int gv100_bios_preos_wait_for_halt(struct gk20a *g);
#endif
#endif /* NVGPU_BIOS_SW_GV100_H */

12
drivers/gpu/nvgpu/tu104/bios_tu104.c → drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,10 +25,8 @@
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include "tu104/bios_tu104.h"
#include "gp106/bios_gp106.h"
#include "nvgpu/hw/tu104/hw_gc6_tu104.h"
#include "bios_sw_tu104.h"
#include "bios_sw_gp106.h"
#define NV_DEVINIT_VERIFY_TIMEOUT_MS 1000U
#define NV_DEVINIT_VERIFY_TIMEOUT_DELAY_US 10U
@@ -42,6 +40,7 @@ int tu104_bios_verify_devinit(struct gk20a *g)
{
struct nvgpu_timeout timeout;
u32 val;
u32 aon_secure_scratch_reg;
int err;
err = nvgpu_timeout_init(g, &timeout, NV_DEVINIT_VERIFY_TIMEOUT_MS,
@@ -51,7 +50,8 @@ int tu104_bios_verify_devinit(struct gk20a *g)
}
do {
val = nvgpu_readl(g, gc6_aon_secure_scratch_group_05_r(0));
aon_secure_scratch_reg = g->ops.bios.get_aon_secure_scratch_reg(g, 0);
val = nvgpu_readl(g, aon_secure_scratch_reg);
val &= NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_MASK;
if (val == NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED) {

31
drivers/gpu/nvgpu/common/vbios/bios_sw_tu104.h Normal file
View File

@@ -0,0 +1,31 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_BIOS_SW_TU104_H
#define NVGPU_BIOS_SW_TU104_H
struct gk20a;
int tu104_bios_verify_devinit(struct gk20a *g);
int tu104_bios_init(struct gk20a *g);
#endif /* NVGPU_BIOS_SW_TU104_H */

104
drivers/gpu/nvgpu/common/vbios/nvlink_bios.c Normal file
View File

@@ -0,0 +1,104 @@
/*
* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/nvlink_bios.h>
#include <nvgpu/string.h>
#include <nvgpu/bios.h>
int nvgpu_bios_get_nvlink_config_data(struct gk20a *g)
{
int ret = 0;
struct nvlink_config_data_hdr_v1 config;
if (g->bios.nvlink_config_data_offset == 0U) {
return -EINVAL;
}
nvgpu_memcpy((u8 *)&config,
&g->bios.data[g->bios.nvlink_config_data_offset],
sizeof(config));
if (config.version != NVLINK_CONFIG_DATA_HDR_VER_10) {
nvgpu_err(g, "unsupported nvlink bios version: 0x%x",
config.version);
return -EINVAL;
}
switch (config.hdr_size) {
case NVLINK_CONFIG_DATA_HDR_12_SIZE:
g->nvlink.ac_coupling_mask = config.ac_coupling_mask;
g->nvlink.train_at_boot = config.train_at_boot;
g->nvlink.link_disable_mask = config.link_disable_mask;
g->nvlink.link_mode_mask = config.link_mode_mask;
g->nvlink.link_refclk_mask = config.link_refclk_mask;
break;
case NVLINK_CONFIG_DATA_HDR_11_SIZE:
g->nvlink.train_at_boot = config.train_at_boot;
g->nvlink.link_disable_mask = config.link_disable_mask;
g->nvlink.link_mode_mask = config.link_mode_mask;
g->nvlink.link_refclk_mask = config.link_refclk_mask;
break;
case NVLINK_CONFIG_DATA_HDR_10_SIZE:
g->nvlink.link_disable_mask = config.link_disable_mask;
g->nvlink.link_mode_mask = config.link_mode_mask;
g->nvlink.link_refclk_mask = config.link_refclk_mask;
break;
default:
nvgpu_err(g, "invalid nvlink bios config size");
ret = -EINVAL;
break;
}
return ret;
}
int nvgpu_bios_get_lpwr_nvlink_table_hdr(struct gk20a *g)
{
struct lpwr_nvlink_table_hdr_v1 hdr;
u8 *lpwr_nvlink_tbl_hdr_ptr = NULL;
lpwr_nvlink_tbl_hdr_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
g->bios.perf_token,
LPWR_NVLINK_TABLE);
if (lpwr_nvlink_tbl_hdr_ptr == NULL) {
nvgpu_err(g, "Invalid pointer to LPWR_NVLINK_TABLE\n");
return -EINVAL;
}
nvgpu_memcpy((u8 *)&hdr, lpwr_nvlink_tbl_hdr_ptr,
LPWR_NVLINK_TABLE_10_HDR_SIZE_06);
if (hdr.version != LWPR_NVLINK_TABLE_10_HDR_VER_10) {
nvgpu_err(g, "Unsupported LPWR_NVLINK_TABLE version: 0x%x",
hdr.version);
return -EINVAL;
}
g->nvlink.initpll_ordinal =
BIOS_GET_FIELD(u8, hdr.line_rate_initpll_ordinal,
VBIOS_LPWR_NVLINK_TABLE_HDR_INITPLL_ORDINAL);
nvgpu_log(g, gpu_dbg_nvlink, " Nvlink initpll_ordinal: 0x%x",
g->nvlink.initpll_ordinal);
return 0;
}

2
drivers/gpu/nvgpu/common/xve/xve_gp106.c
View File

@@ -26,7 +26,7 @@
#include <nvgpu/timers.h>
#include <nvgpu/gk20a.h>
#include "gp106/bios_gp106.h"
#include "common/vbios/bios_sw_gp106.h"
#include "xve_gp106.h"

31
drivers/gpu/nvgpu/hal/bios/bios_tu104.c Normal file
View File

@@ -0,0 +1,31 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "nvgpu/hw/tu104/hw_gc6_tu104.h"
#include "bios_tu104.h"
u32 tu104_get_aon_secure_scratch_reg(struct gk20a *g, u32 i)
{
return gc6_aon_secure_scratch_group_05_r(i);
}

9
drivers/gpu/nvgpu/tu104/bios_tu104.h → drivers/gpu/nvgpu/hal/bios/bios_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -23,9 +23,10 @@
#ifndef NVGPU_BIOS_TU104_H
#define NVGPU_BIOS_TU104_H
#include <nvgpu/types.h>
struct gk20a;
int tu104_bios_verify_devinit(struct gk20a *g);
int tu104_bios_init(struct gk20a *g);
u32 tu104_get_aon_secure_scratch_reg(struct gk20a *g, u32 i);
#endif /* NVGPU_BIOS_TU104_H */
#endif /*NVGPU_BIOS_TU104_H */

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -92,9 +92,9 @@
#include "hal/falcon/falcon_gk20a.h"
#include "hal/perf/perf_gm20b.h"
#include "hal/netlist/netlist_gm20b.h"
#include "hal/top/top_gm20b.h"
#include "hal/clk/clk_gm20b.h"
#include "common/top/top_gm20b.h"
#include "common/fifo/channel_gk20a.h"
#include "common/fifo/channel_gm20b.h"
#include "common/pmu/pg/pg_sw_gm20b.h"

4
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -111,11 +111,11 @@
#include "hal/falcon/falcon_gk20a.h"
#include "hal/perf/perf_gm20b.h"
#include "hal/netlist/netlist_gp10b.h"
#include "hal/top/top_gm20b.h"
#include "hal/top/top_gp10b.h"
#include "common/pmu/pg/pg_sw_gm20b.h"
#include "common/pmu/pg/pg_sw_gp10b.h"
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"
#include "common/fifo/channel_gk20a.h"
#include "common/fifo/channel_gm20b.h"
#include "common/clk_arb/clk_arb_gp10b.h"

21
drivers/gpu/nvgpu/hal/init/hal_gv100.c
View File

@@ -125,12 +125,14 @@
#include "hal/sync/syncpt_cmdbuf_gv11b.h"
#include "hal/sync/sema_cmdbuf_gv11b.h"
#include "hal/netlist/netlist_gv100.h"
#include "hal/top/top_gm20b.h"
#include "hal/top/top_gp10b.h"
#include "hal/top/top_gp106.h"
#include "hal/top/top_gv100.h"
#include "hal/top/top_gv11b.h"
#include "common/xve/xve_gp106.h"
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"
#include "common/top/top_gv100.h"
#include "common/top/top_gv11b.h"
#include "common/nvlink/init/device_reginit_gv100.h"
#include "common/nvlink/intr_and_err_handling_gv100.h"
#include "hal/nvlink/minion_gv100.h"
@@ -141,17 +143,18 @@
#include "common/fifo/channel_gm20b.h"
#include "common/fifo/channel_gv11b.h"
#include "common/fifo/channel_gv100.h"
#include "common/vbios/bios_sw_gp106.h"
#include "common/vbios/bios_sw_gv100.h"
#include "gm20b/mm_gm20b.h"
#include "gp106/bios_gp106.h"
#include "gp10b/mm_gp10b.h"
#include "gv11b/mm_gv11b.h"
#include "hal_gv100.h"
#include "gv100/bios_gv100.h"
#include "gv100/mm_gv100.h"
#include "hal/clk/clk_gv100.h"
@@ -1454,6 +1457,10 @@ static const struct gpu_ops gv100_ops = {
.get_max_ltc_per_fbp = gm20b_top_get_max_ltc_per_fbp,
.get_max_lts_per_ltc = gm20b_top_get_max_lts_per_ltc,
.get_num_lce = gv11b_top_get_num_lce,
.read_top_scratch1_reg = gp106_top_read_scratch1_reg,
.top_scratch1_devinit_completed =
gp106_top_scratch1_devinit_completed,
},
.sec2 = {
.falcon_base_addr = gp106_sec2_falcon_base_addr,

7
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -124,13 +124,14 @@
#include "hal/falcon/falcon_gk20a.h"
#include "hal/perf/perf_gv11b.h"
#include "hal/netlist/netlist_gv11b.h"
#include "hal/top/top_gm20b.h"
#include "hal/top/top_gp10b.h"
#include "hal/top/top_gv11b.h"
#include "common/pmu/pg/pg_sw_gm20b.h"
#include "common/pmu/pg/pg_sw_gp106.h"
#include "common/pmu/pg/pg_sw_gv11b.h"
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"
#include "common/top/top_gv11b.h"
#include "common/fifo/channel_gk20a.h"
#include "common/fifo/channel_gm20b.h"
#include "common/fifo/channel_gv11b.h"

15
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -135,12 +135,14 @@
#include "hal/sync/syncpt_cmdbuf_gv11b.h"
#include "hal/sync/sema_cmdbuf_gv11b.h"
#include "hal/netlist/netlist_tu104.h"
#include "hal/top/top_gm20b.h"
#include "hal/top/top_gp10b.h"
#include "hal/top/top_gv100.h"
#include "hal/top/top_gv11b.h"
#include "hal/bios/bios_tu104.h"
#include "common/xve/xve_gp106.h"
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"
#include "common/top/top_gv100.h"
#include "common/top/top_gv11b.h"
#include "common/nvlink/init/device_reginit_gv100.h"
#include "common/nvlink/intr_and_err_handling_gv100.h"
#include "hal/nvlink/minion_gv100.h"
@@ -161,13 +163,15 @@
#include "hal/clk/clk_gv100.h"
#include "common/vbios/bios_sw_gp106.h"
#include "common/vbios/bios_sw_tu104.h"
#include "gp10b/mm_gp10b.h"
#include "gv11b/mm_gv11b.h"
#include "tu104/mm_tu104.h"
#include "tu104/fifo_tu104.h"
#include "tu104/bios_tu104.h"
#include "hal/fbpa/fbpa_tu104.h"
#include "hal_tu104.h"
@@ -367,6 +371,7 @@ static const struct gpu_ops tu104_ops = {
.devinit = NULL,
.preos = NULL,
.verify_devinit = tu104_bios_verify_devinit,
.get_aon_secure_scratch_reg = tu104_get_aon_secure_scratch_reg,
},
.ltc = {
.determine_L2_size_bytes = gp10b_determine_L2_size_bytes,

2
drivers/gpu/nvgpu/common/top/top_gm20b.c → drivers/gpu/nvgpu/hal/top/top_gm20b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

6
drivers/gpu/nvgpu/common/top/top_gm20b.h → drivers/gpu/nvgpu/hal/top/top_gm20b.h
View File

@@ -1,7 +1,5 @@
/*
* GM20B TOP UNIT
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,6 +18,8 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* GM20B TOP UNIT
*/
#ifndef TOP_GM20B_H

37
drivers/gpu/nvgpu/hal/top/top_gp106.c Normal file
View File

@@ -0,0 +1,37 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/io.h>
#include <nvgpu/hw/gp106/hw_top_gp106.h>
#include "top_gp106.h"
u32 gp106_top_read_scratch1_reg(struct gk20a *g)
{
return gk20a_readl(g, top_scratch1_r());
}
u32 gp106_top_scratch1_devinit_completed(struct gk20a *g, u32 value)
{
return top_scratch1_devinit_completed_v(value);
}

35
drivers/gpu/nvgpu/hal/top/top_gp106.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* GP106 TOP UNIT
*/
#ifndef TOP_GP106_H
#define TOP_GP106_H
#include <nvgpu/types.h>
struct gk20a;
u32 gp106_top_read_scratch1_reg(struct gk20a *g);
u32 gp106_top_scratch1_devinit_completed(struct gk20a *g, u32 value);
#endif /*TOP_GP106_H */

2
drivers/gpu/nvgpu/common/top/top_gp10b.c → drivers/gpu/nvgpu/hal/top/top_gp10b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

7
drivers/gpu/nvgpu/common/top/top_gp10b.h → drivers/gpu/nvgpu/hal/top/top_gp10b.h
View File

@@ -1,7 +1,5 @@
/*
* GP10B TOP UNIT
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,6 +18,8 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* GP10B TOP UNIT
*/
#ifndef TOP_GP10B_H
@@ -36,4 +36,5 @@ u32 gp10b_get_num_engine_type_entries(struct gk20a *g, u32 engine_type);
int gp10b_get_device_info(struct gk20a *g, struct nvgpu_device_info *dev_info,
u32 engine_type, u32 inst_id);
bool gp10b_is_engine_ce(struct gk20a *g, u32 engine_type);
#endif

5
drivers/gpu/nvgpu/common/top/top_gv100.c → drivers/gpu/nvgpu/hal/top/top_gv100.c
View File

@@ -1,7 +1,5 @@
/*
* GV100 TOP UNIT
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,6 +18,7 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#include <nvgpu/io.h>

5
drivers/gpu/nvgpu/common/top/top_gv100.h → drivers/gpu/nvgpu/hal/top/top_gv100.h
View File

@@ -1,7 +1,5 @@
/*
* GV100 TOP UNIT
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,6 +18,7 @@
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#ifndef TOP_GV100_H

0
drivers/gpu/nvgpu/common/top/top_gv11b.c → drivers/gpu/nvgpu/hal/top/top_gv11b.c
View File

0
drivers/gpu/nvgpu/common/top/top_gv11b.h → drivers/gpu/nvgpu/hal/top/top_gv11b.h
View File

227
drivers/gpu/nvgpu/include/nvgpu/bios.h
View File

@@ -1166,6 +1166,230 @@ struct nvgpu_bios_lpwr_gr_table_1x_entry {
#define VBIOS_LPWR_NVLINK_TABLE_HDR_INITPLL_ORDINAL_MASK 0x07U
#define VBIOS_LPWR_NVLINK_TABLE_HDR_INITPLL_ORDINAL_SHIFT 0x00U
#define BIT_HEADER_ID 0xb8ffU
#define BIT_HEADER_SIGNATURE 0x00544942U
#define PCI_EXP_ROM_SIG 0xaa55U
#define PCI_EXP_ROM_SIG_NV 0x4e56U
#define INIT_DONE 0x71U
#define INIT_RESUME 0x72U
#define INIT_CONDITION 0x75U
#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8fU
#define PCI_ROM_IMAGE_BLOCK_SIZE 512U
#define PCI_DATA_STRUCTURE_CODE_TYPE_VBIOS_BASE 0x00U
#define PCI_DATA_STRUCTURE_CODE_TYPE_VBIOS_UEFI 0x03U
struct bios_bit {
u16 id;
u32 signature;
u16 bcd_version;
u8 header_size;
u8 token_size;
u8 token_entries;
u8 header_checksum;
} __packed;
#define TOKEN_ID_BIOSDATA 0x42U
#define TOKEN_ID_NVINIT_PTRS 0x49U
#define TOKEN_ID_FALCON_DATA 0x70U
#define TOKEN_ID_PERF_PTRS 0x50U
#define TOKEN_ID_CLOCK_PTRS 0x43U
#define TOKEN_ID_VIRT_PTRS 0x56U
#define TOKEN_ID_MEMORY_PTRS 0x4DU
#define MEMORY_PTRS_V1 1U
#define MEMORY_PTRS_V2 2U
struct memory_ptrs_v1 {
u8 rsvd0[2];
u8 mem_strap_data_count;
u16 mem_strap_xlat_tbl_ptr;
u8 rsvd1[8];
} __packed;
struct memory_ptrs_v2 {
u8 mem_strap_data_count;
u16 mem_strap_xlat_tbl_ptr;
u8 rsvd[14];
} __packed;
struct biosdata {
u32 version;
u8 oem_version;
u8 checksum;
u16 int15callbackspost;
u16 int16callbackssystem;
u16 boardid;
u16 framecount;
u8 biosmoddate[8];
} __packed;
struct nvinit_ptrs {
u16 initscript_table_ptr;
u16 macro_index_table_ptr;
u16 macro_table_ptr;
u16 condition_table_ptr;
u16 io_condition_table_ptr;
u16 io_flag_condition_table_ptr;
u16 init_function_table_ptr;
u16 vbios_private_table_ptr;
u16 data_arrays_table_ptr;
u16 pcie_settings_script_ptr;
u16 devinit_tables_ptr;
u16 devinit_tables_size;
u16 bootscripts_ptr;
u16 bootscripts_size;
u16 nvlink_config_data_ptr;
} __packed;
struct falcon_data_v2 {
u32 falcon_ucode_table_ptr;
} __packed;
struct falcon_ucode_table_hdr_v1 {
u8 version;
u8 header_size;
u8 entry_size;
u8 entry_count;
u8 desc_version;
u8 desc_size;
} __packed;
struct falcon_ucode_table_entry_v1 {
u8 application_id;
u8 target_id;
u32 desc_ptr;
} __packed;
#define TARGET_ID_PMU 0x01U
#define APPLICATION_ID_DEVINIT 0x04U
#define APPLICATION_ID_PRE_OS 0x01U
#define FALCON_UCODE_FLAGS_VERSION_AVAILABLE 0x1U
#define FALCON_UCODE_IS_VERSION_AVAILABLE(hdr) \
(((hdr).v2.v_desc & FALCON_UCODE_FLAGS_VERSION_AVAILABLE) == \
FALCON_UCODE_FLAGS_VERSION_AVAILABLE)
/*
* version is embedded in bits 8:15 of the header on version 2+
* and the header length in bits 16:31
*/
#define FALCON_UCODE_GET_VERSION(hdr) \
U8(((hdr).v2.v_desc >> 8) & 0xffU)
#define FALCON_UCODE_GET_DESC_SIZE(hdr) \
U16(((hdr).v2.v_desc >> 16) & 0xffffU)
struct falcon_ucode_desc_v1 {
union {
u32 v_desc;
u32 stored_size;
} hdr_size;
u32 uncompressed_size;
u32 virtual_entry;
u32 interface_offset;
u32 imem_phys_base;
u32 imem_load_size;
u32 imem_virt_base;
u32 imem_sec_base;
u32 imem_sec_size;
u32 dmem_offset;
u32 dmem_phys_base;
u32 dmem_load_size;
} __packed;
struct falcon_ucode_desc_v2 {
u32 v_desc;
u32 stored_size;
u32 uncompressed_size;
u32 virtual_entry;
u32 interface_offset;
u32 imem_phys_base;
u32 imem_load_size;
u32 imem_virt_base;
u32 imem_sec_base;
u32 imem_sec_size;
u32 dmem_offset;
u32 dmem_phys_base;
u32 dmem_load_size;
u32 alt_imem_load_size;
u32 alt_dmem_load_size;
} __packed;
union falcon_ucode_desc {
struct falcon_ucode_desc_v1 v1;
struct falcon_ucode_desc_v2 v2;
};
struct application_interface_table_hdr_v1 {
u8 version;
u8 header_size;
u8 entry_size;
u8 entry_count;
} __packed;
struct application_interface_entry_v1 {
u32 id;
u32 dmem_offset;
} __packed;
#define APPINFO_ID_DEVINIT 0x01U
#define APPINFO_ID_DEVINIT 0x01U
struct devinit_engine_interface {
u16 version;
u16 size;
u16 application_version;
u16 application_features;
u32 tables_phys_base;
u32 tables_virt_base;
u32 script_phys_base;
u32 script_virt_base;
u32 script_virt_entry;
u16 script_size;
u8 memory_strap_count;
u8 reserved;
u32 memory_information_table_virt_base;
u32 empty_script_virt_base;
u32 cond_table_virt_base;
u32 io_cond_table_virt_base;
u32 data_arrays_table_virt_base;
u32 gpio_assignment_table_virt_base;
} __packed;
struct pci_exp_rom {
u16 sig;
u8 reserved[0x16];
u16 pci_data_struct_ptr;
u32 size_of_block;
} __packed;
struct pci_data_struct {
u32 sig;
u16 vendor_id;
u16 device_id;
u16 device_list_ptr;
u16 pci_data_struct_len;
u8 pci_data_struct_rev;
u8 class_code[3];
u16 image_len;
u16 vendor_rom_rev;
u8 code_type;
u8 last_image;
u16 max_runtime_image_len;
} __packed;
struct pci_ext_data_struct {
u32 sig;
u16 nv_pci_data_ext_rev;
u16 nv_pci_data_ext_len;
u16 sub_image_len;
u8 priv_last_image;
u8 flags;
} __packed;
int nvgpu_bios_parse_rom(struct gk20a *g);
u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset);
s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset);
@@ -1173,6 +1397,5 @@ u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset);
u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset);
void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
struct bit_token *ptoken, u8 table_id);
int nvgpu_bios_get_nvlink_config_data(struct gk20a *g);
int nvgpu_bios_get_lpwr_nvlink_table_hdr(struct gk20a *g);
#endif

4
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1626,6 +1626,7 @@ struct gpu_ops {
int (*devinit)(struct gk20a *g);
int (*preos)(struct gk20a *g);
int (*verify_devinit)(struct gk20a *g);
u32 (*get_aon_secure_scratch_reg)(struct gk20a *g, u32 i);
} bios;
#if defined(CONFIG_GK20A_CYCLE_STATS)
@@ -1829,6 +1830,9 @@ struct gpu_ops {
u32 (*get_max_ltc_per_fbp)(struct gk20a *g);
u32 (*get_max_lts_per_ltc)(struct gk20a *g);
u32 (*get_num_lce)(struct gk20a *g);
u32 (*read_top_scratch1_reg)(struct gk20a *g);
u32 (*top_scratch1_devinit_completed)(struct gk20a *g,
u32 value);
} top;
struct {
void (*secured_sec2_start)(struct gk20a *g);

61
drivers/gpu/nvgpu/include/nvgpu/nvlink_bios.h Normal file
View File

@@ -0,0 +1,61 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NVLINK_BIOS_H
#define NVGPU_NVLINK_BIOS_H
#include <nvgpu/types.h>
#define NVLINK_CONFIG_DATA_HDR_VER_10 0x1U
#define NVLINK_CONFIG_DATA_HDR_10_SIZE 16U
#define NVLINK_CONFIG_DATA_HDR_11_SIZE 17U
#define NVLINK_CONFIG_DATA_HDR_12_SIZE 21U
struct nvlink_config_data_hdr_v1 {
u8 version;
u8 hdr_size;
u16 rsvd0;
u32 link_disable_mask;
u32 link_mode_mask;
u32 link_refclk_mask;
u8 train_at_boot;
u32 ac_coupling_mask;
} __packed;
#define LWPR_NVLINK_TABLE_10_HDR_VER_10 0x10U
#define LPWR_NVLINK_TABLE_10_HDR_SIZE_06 6U
struct lpwr_nvlink_table_hdr_v1 {
u8 version;
u8 hdr_size;
u8 entry_size;
u8 entry_count;
u8 default_entry_idx;
u8 line_rate_initpll_ordinal;
} __packed;
struct gk20a;
int nvgpu_bios_get_nvlink_config_data(struct gk20a *g);
int nvgpu_bios_get_lpwr_nvlink_table_hdr(struct gk20a *g);
#endif