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gpu: nvgpu: compile out FENCES from safety build
Add CONFIG_NVGPU_FENCE safety build flag to compile out common/fence/fence.c from safety build. Jira NVGPU-3429 Change-Id: I726b3aa85fee26e314ed1677b9a0df284ccd7c45 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2143512 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -80,6 +80,9 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_CHANNEL_WDT
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CONFIG_NVGPU_KERNEL_MODE_SUBMIT := 1
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NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_KERNEL_MODE_SUBMIT
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# Enable fences for safety build till until we switch to user mode submits only
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CONFIG_NVGPU_FENCE := 1
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NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
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# Enable Channel/TSG Scheduling for safety build until devctl whitelisting is done
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@@ -146,7 +146,6 @@ srcs += common/utils/enabled.c \
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common/fifo/pbdma_status.c \
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common/fifo/userd.c \
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common/mc/mc.c \
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common/fence/fence.c \
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hal/mc/mc_gm20b.c \
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hal/mc/mc_gp10b.c \
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hal/bus/bus_gk20a.c \
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@@ -383,6 +382,10 @@ srcs += common/fifo/submit.c \
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hal/sync/sema_cmdbuf_gv11b.c
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endif
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ifeq ($(CONFIG_NVGPU_FENCE),1)
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srcs += common/fence/fence.c
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endif
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ifeq ($(CONFIG_NVGPU_FECS_TRACE),1)
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srcs += common/gr/fecs_trace.c \
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hal/gr/fecs_trace/fecs_trace_gm20b.c \
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