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gpu: nvgpu: update l2 sector promotion logic

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L2 sector promotion setup in cfg2_vidmem and cfg3_sysmem registers was
verified by comparing full register values after writing. However that
fails as some of the bits like VIDMEM_SP2_256B_PROMOTE_ON_SECT0 in cfg2
and SYSMEM_PROMOTE_ENABLE, FETCH_PARTIAL_CATOM_32B in cfg3 are set
on setting promotion.

Just compare the promotions bits for L1 and T1 in the cfg registers.

Bug 3634348

Change-Id: I53c0a0a7bbe776a000a386524759d7277a015054
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2779619
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sagar Kamble
2022-09-21 22:15:25 +05:30
committed by mobile promotions
parent 4315132e7d
commit b48892ea33
1 changed files with 26 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/gpu/nvgpu/hal/ltc/ltc_tu104.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -161,12 +161,33 @@ int tu104_set_l2_sector_promotion(struct gk20a *g, struct nvgpu_tsg *tsg,
nvgpu_err(g, "failed to read ltcs_ltss_tstg_cfg(2,3)_r");
goto fail;
}
if (cfg2_vidmem != cfg_ops[0].value_lo || cfg3_sysmem != cfg_ops[1].value_lo) {
if ((get_field(cfg2_vidmem,
ltc_ltcs_ltss_tstg_cfg2_vidmem_t1_promote_m()) !=
get_field(cfg_ops[0].value_lo,
ltc_ltcs_ltss_tstg_cfg2_vidmem_t1_promote_m())) ||
(get_field(cfg2_vidmem,
ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_m()) !=
get_field(cfg_ops[0].value_lo,
ltc_ltcs_ltss_tstg_cfg2_vidmem_l1_promote_m()))) {
nvgpu_err(g, "mismatch: cfg2: wrote(0x%x) read(0x%x)",
cfg_ops[0].value_lo, cfg2_vidmem);
nvgpu_err(g, " cfg3: wrote(0x%x) read(0x%x)",
cfg_ops[1].value_lo, cfg3_sysmem);
cfg2_vidmem, cfg_ops[0].value_lo);
err = -EINVAL;
goto fail;
}
if ((get_field(cfg3_sysmem,
ltc_ltcs_ltss_tstg_cfg3_sysmem_t1_promote_m()) !=
get_field(cfg_ops[1].value_lo,
ltc_ltcs_ltss_tstg_cfg3_sysmem_t1_promote_m())) ||
(get_field(cfg3_sysmem,
ltc_ltcs_ltss_tstg_cfg3_sysmem_l1_promote_m()) !=
get_field(cfg_ops[1].value_lo,
ltc_ltcs_ltss_tstg_cfg3_sysmem_l1_promote_m()))) {
nvgpu_err(g, "mismatch: cfg3: wrote(0x%x) read(0x%x)",
cfg3_sysmem, cfg_ops[1].value_lo);
err = -EINVAL;
goto fail;
}
fail: