gpu: nvgpu: Update POSIX BIT() macro to ULL

For most of the builds we have in GVS userspace is 64 bits. But
it seems like at least some L4T userspace builds are either not
32 bits or have an UL that only covers 32 bits. This is seen in
GVS:

/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gv11b/mm_gv11b.c: In function 'gv11b_gpu_phys_addr':
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gv11b/mm_gv11b.c:273:3: error: left shift count >= width of type
make[2]: *** [/dvs/git/dirty/git-master_modular/tmake/artifacts/CommonRules.tmk:318: mm_gv11b.o] Error 1

This patch simply bumps the UL to ULL in BIT() to make sure that
we always have at least 64 bits available for the BIT() macro.

JIRA NVGPU-525

Change-Id: I67de4338afc5bee4f1fa16faee6116e0e7dbf108
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1718564
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2018-05-14 10:54:22 -07:00
committed by mobile promotions
parent 4654d9abd1
commit b4f8cd76e2

View File

@@ -33,7 +33,7 @@
#define BITS_TO_LONGS(bits) \
(bits + (BITS_PER_LONG - 1) / BITS_PER_LONG)
#define BIT(i) (1UL << (i))
#define BIT(i) (1ULL << (i))
#define GENMASK(h, l) \
(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))