gpu: nvgpu: posix: add register/unregister reg space

For some units, we want to use register spaces with
data already initialized with power-on register values.

Added the following routines:
- nvgpu_posix_io_register_reg_space
- nvgpu_posix_io_unregister_reg_space

Jira NVGPU-3476

Change-Id: Id4f5beb5e5d6b4af795e2eb58ccee13d2cfa6da5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120563
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-05-16 14:33:39 -07:00
committed by mobile promotions
parent 11630ad56f
commit b528bb5ae4
2 changed files with 40 additions and 6 deletions

View File

@@ -85,10 +85,21 @@ nvgpu_posix_io_reg_space_from_link(struct nvgpu_list_node *node)
void nvgpu_posix_io_init_reg_space(struct gk20a *g);
int nvgpu_posix_io_get_error_code(struct gk20a *g);
void nvgpu_posix_io_reset_error_code(struct gk20a *g);
/* allocate and register reg_space */
int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size);
int nvgpu_posix_io_add_reg_space_ext(struct gk20a *g, u32 base, u32 size,
u32 *data);
struct nvgpu_posix_io_reg_space *nvgpu_posix_io_get_reg_space(struct gk20a *g,
u32 addr);
void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base);
/* register/unregister pre-initialized reg_space */
int nvgpu_posix_io_register_reg_space(struct gk20a *g,
struct nvgpu_posix_io_reg_space *reg_space);
void nvgpu_posix_io_unregister_reg_space(struct gk20a *g,
struct nvgpu_posix_io_reg_space *reg_space);
void nvgpu_posix_io_writel_reg_space(struct gk20a *g, u32 addr, u32 data);
u32 nvgpu_posix_io_readl_reg_space(struct gk20a *g, u32 addr);

View File

@@ -201,12 +201,34 @@ void nvgpu_posix_io_reset_error_code(struct gk20a *g)
}
/*
* Add a new register space to the list of spaces, defined by a base
* address and a size.
* Register a pre-initialized register space to the list of spaces.
* This allows registering a space with statically initialized data.
*/
int nvgpu_posix_io_register_reg_space(struct gk20a *g,
struct nvgpu_posix_io_reg_space *reg_space)
{
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
if (reg_space == NULL || reg_space->data == NULL) {
return -ENOMEM;
}
nvgpu_list_add_tail(&reg_space->link, &p->reg_space_head);
return 0;
}
void nvgpu_posix_io_unregister_reg_space(struct gk20a *g,
struct nvgpu_posix_io_reg_space *reg_space)
{
nvgpu_list_del(&reg_space->link);
}
/*
* Allocate and register a new register space to the list of spaces,
* defined by a base address and a size.
*/
int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size)
{
struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
struct nvgpu_posix_io_reg_space *new_reg_space =
nvgpu_kzalloc(g, sizeof(struct nvgpu_posix_io_reg_space));
@@ -219,11 +241,11 @@ int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size)
new_reg_space->data = nvgpu_vzalloc(g, size);
if (new_reg_space->data == NULL) {
nvgpu_vfree(g, new_reg_space);
return -ENOMEM;
}
nvgpu_list_add_tail(&new_reg_space->link, &p->reg_space_head);
return 0;
return nvgpu_posix_io_register_reg_space(g, new_reg_space);
}
void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base)
@@ -234,7 +256,8 @@ void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base)
/* Invalid space, or already de-allocated */
return;
}
nvgpu_list_del(&reg_space->link);
nvgpu_posix_io_unregister_reg_space(g, reg_space);
nvgpu_vfree(g, reg_space->data);
nvgpu_kfree(g, reg_space);
}