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gpu: nvgpu: posix: add register/unregister reg space
For some units, we want to use register spaces with data already initialized with power-on register values. Added the following routines: - nvgpu_posix_io_register_reg_space - nvgpu_posix_io_unregister_reg_space Jira NVGPU-3476 Change-Id: Id4f5beb5e5d6b4af795e2eb58ccee13d2cfa6da5 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2120563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -85,10 +85,21 @@ nvgpu_posix_io_reg_space_from_link(struct nvgpu_list_node *node)
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void nvgpu_posix_io_init_reg_space(struct gk20a *g);
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int nvgpu_posix_io_get_error_code(struct gk20a *g);
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void nvgpu_posix_io_reset_error_code(struct gk20a *g);
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/* allocate and register reg_space */
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int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size);
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int nvgpu_posix_io_add_reg_space_ext(struct gk20a *g, u32 base, u32 size,
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u32 *data);
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struct nvgpu_posix_io_reg_space *nvgpu_posix_io_get_reg_space(struct gk20a *g,
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u32 addr);
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void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base);
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/* register/unregister pre-initialized reg_space */
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int nvgpu_posix_io_register_reg_space(struct gk20a *g,
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struct nvgpu_posix_io_reg_space *reg_space);
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void nvgpu_posix_io_unregister_reg_space(struct gk20a *g,
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struct nvgpu_posix_io_reg_space *reg_space);
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void nvgpu_posix_io_writel_reg_space(struct gk20a *g, u32 addr, u32 data);
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u32 nvgpu_posix_io_readl_reg_space(struct gk20a *g, u32 addr);
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@@ -201,12 +201,34 @@ void nvgpu_posix_io_reset_error_code(struct gk20a *g)
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}
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/*
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* Add a new register space to the list of spaces, defined by a base
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* address and a size.
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* Register a pre-initialized register space to the list of spaces.
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* This allows registering a space with statically initialized data.
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*/
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int nvgpu_posix_io_register_reg_space(struct gk20a *g,
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struct nvgpu_posix_io_reg_space *reg_space)
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{
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struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
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if (reg_space == NULL || reg_space->data == NULL) {
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return -ENOMEM;
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}
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nvgpu_list_add_tail(®_space->link, &p->reg_space_head);
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return 0;
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}
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void nvgpu_posix_io_unregister_reg_space(struct gk20a *g,
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struct nvgpu_posix_io_reg_space *reg_space)
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{
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nvgpu_list_del(®_space->link);
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}
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/*
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* Allocate and register a new register space to the list of spaces,
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* defined by a base address and a size.
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*/
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int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size)
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{
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struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
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struct nvgpu_posix_io_reg_space *new_reg_space =
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nvgpu_kzalloc(g, sizeof(struct nvgpu_posix_io_reg_space));
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@@ -219,11 +241,11 @@ int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size)
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new_reg_space->data = nvgpu_vzalloc(g, size);
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if (new_reg_space->data == NULL) {
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nvgpu_vfree(g, new_reg_space);
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return -ENOMEM;
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}
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nvgpu_list_add_tail(&new_reg_space->link, &p->reg_space_head);
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return 0;
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return nvgpu_posix_io_register_reg_space(g, new_reg_space);
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}
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void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base)
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@@ -234,7 +256,8 @@ void nvgpu_posix_io_delete_reg_space(struct gk20a *g, u32 base)
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/* Invalid space, or already de-allocated */
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return;
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}
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nvgpu_list_del(®_space->link);
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nvgpu_posix_io_unregister_reg_space(g, reg_space);
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nvgpu_vfree(g, reg_space->data);
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nvgpu_kfree(g, reg_space);
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}
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