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gpu: nvgpu: Cleanup unused variables

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There are numerous places where variables are assigned to but then
never used. This patch cleans up all these unused variables and
in some cases simplifies surrounding logic.

Also delete unused header includes and add necessary header includes.

JIRA NVGPU-525

Signed-off-by: Alex Waterman <alexw@nvidia.com>
Change-Id: Ice9ec2a0e97f262d0dcfebe22f83208dbea569d9
Reviewed-on: https://git-master.nvidia.com/r/1662548
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2018-02-21 15:59:56 -08:00
committed by mobile promotions
parent bd95c2ce3f
commit b5d3cf444e
6 changed files with 13 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1215,9 +1215,7 @@ void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
{
struct fifo_gk20a *f = NULL;
u32 engine_enum = ENGINE_INVAL_GK20A;
u32 inst_id = 0;
struct fifo_engine_info_gk20a *engine_info;
gk20a_dbg_fn("");
@@ -1225,14 +1223,10 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
if (!g)
return;
f = &g->fifo;
engine_info = gk20a_fifo_get_engine_info(g, engine_id);
if (engine_info) {
if (engine_info)
engine_enum = engine_info->engine_enum;
inst_id = engine_info->inst_id;
}
if (engine_enum == ENGINE_INVAL_GK20A)
nvgpu_err(g, "unsupported engine_id %d", engine_id);
@@ -1300,19 +1294,15 @@ bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,
u32 engine_subid, bool fake_fault)
{
u32 engine_enum = ENGINE_INVAL_GK20A;
struct fifo_gk20a *fifo = NULL;
struct fifo_engine_info_gk20a *engine_info;
if (!g)
return false;
fifo = &g->fifo;
engine_info = gk20a_fifo_get_engine_info(g, engine_id);
if (engine_info) {
if (engine_info)
engine_enum = engine_info->engine_enum;
}
if (engine_enum == ENGINE_INVAL_GK20A)
return false;
@@ -2974,7 +2964,6 @@ static void gk20a_fifo_runlist_reset_engines(struct gk20a *g, u32 runlist_id)
static int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
{
struct fifo_runlist_info_gk20a *runlist;
struct nvgpu_timeout timeout;
unsigned long delay = GR_IDLE_CHECK_DEFAULT;
int ret = -ETIMEDOUT;
@@ -2982,7 +2971,6 @@ static int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
NVGPU_TIMER_CPU_TIMER);
runlist = &g->fifo.runlist_info[runlist_id];
do {
if ((gk20a_readl(g, fifo_eng_runlist_r(runlist_id)) &
fifo_eng_runlist_pending_true_f()) == 0) {
@@ -3173,7 +3161,7 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
struct fifo_runlist_info_gk20a *runlist = NULL;
u32 *runlist_entry_base = NULL;
u64 runlist_iova;
u32 old_buf, new_buf;
u32 new_buf;
struct channel_gk20a *ch = NULL;
struct tsg_gk20a *tsg = NULL;
u32 count = 0;
@@ -3205,7 +3193,6 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
}
}
old_buf = runlist->cur_buffer;
new_buf = !runlist->cur_buffer;
runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[new_buf]);

6
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -22,8 +22,6 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <trace/events/gk20a.h>
#include <nvgpu/dma.h>
#include <nvgpu/kmem.h>
#include <nvgpu/gmmu.h>
@@ -6171,14 +6169,10 @@ static int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
u32 *broadcast_flags)
{
u32 gpc_addr;
u32 ppc_address;
u32 ppc_broadcast_addr;
gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
/* setup defaults */
ppc_address = 0;
ppc_broadcast_addr = 0;
*addr_type = CTXSW_ADDR_TYPE_SYS;
*broadcast_flags = PRI_BROADCAST_FLAGS_NONE;
*gpc_num = 0;

2
drivers/gpu/nvgpu/gk20a/mc_gk20a.c
View File

@@ -22,8 +22,6 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <trace/events/gk20a.h>
#include "gk20a.h"
#include "mc_gk20a.h"

3
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -756,7 +756,7 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
{
u32 err, flags;
u32 err;
u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() -
gr_fecs_falcon_hwcfg_r();
u8 falcon_id_mask = 0;
@@ -770,7 +770,6 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
gr_gpccs_ctxsw_mailbox_value_f(0xc0de7777));
}
flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
g->pmu_lsf_loaded_falcon_id = 0;
if (nvgpu_is_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE)) {
/* this must be recovery so bootstrap fecs and gpccs */

20
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -33,6 +33,7 @@
#include <nvgpu/nvhost.h>
#include <nvgpu/barrier.h>
#include <nvgpu/mm.h>
#include <nvgpu/log2.h>
#include <nvgpu/ctxsw_trace.h>
#include <nvgpu/io_usermode.h>
@@ -932,7 +933,6 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
u32 id, unsigned int id_type, unsigned int rc_type,
struct mmu_fault_info *mmfault)
{
bool verbose = false;
struct tsg_gk20a *tsg = NULL;
struct channel_gk20a *refch = NULL;
u32 runlists_mask, runlist_id;
@@ -1049,22 +1049,18 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
#endif
if (tsg) {
if (!g->fifo.deferred_reset_pending) {
if (rc_type == RC_TYPE_MMU_FAULT) {
gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg);
verbose = gk20a_fifo_error_tsg(g, tsg);
}
}
if (!g->fifo.deferred_reset_pending &&
rc_type == RC_TYPE_MMU_FAULT)
gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg);
gk20a_fifo_abort_tsg(g, tsg->tsgid, false);
if (refch)
gk20a_channel_put(refch);
} else if (refch) {
if (!g->fifo.deferred_reset_pending) {
if (rc_type == RC_TYPE_MMU_FAULT) {
if (!g->fifo.deferred_reset_pending &&
rc_type == RC_TYPE_MMU_FAULT)
gk20a_fifo_set_ctx_mmu_error_ch(g, refch);
verbose = gk20a_fifo_error_ch(g, refch);
}
}
gk20a_channel_abort(refch, false);
gk20a_channel_put(refch);
} else {

4
drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
View File

@@ -184,7 +184,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
struct mm_gk20a *mm = &g->mm;
struct pmu_ucode_desc *desc = pmu->desc;
u64 addr_code_lo, addr_data_lo, addr_load_lo;
u64 addr_code_hi, addr_data_hi, addr_load_hi;
u64 addr_code_hi, addr_data_hi;
u32 i, blocks, addr_args;
gk20a_dbg_fn("");
@@ -238,8 +238,6 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
desc->app_resident_data_offset) >> 8);
addr_load_lo = u64_lo32((pmu->ucode.gpu_va +
desc->bootloader_start_offset) >> 8);
addr_load_hi = u64_hi32((pmu->ucode.gpu_va +
desc->bootloader_start_offset) >> 8);
gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0);
gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0);