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gpu: nvgpu: rename clock_gating ops to cg

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Rename clock_gating ops to cg

JIRA NVGPU-2014

Change-Id: Iae3c5739c1dcecb1fa8364a509b646162b43d2a2
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2082270
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-03-26 15:45:05 -07:00
committed by mobile promotions
parent 57d1d0af03
commit b650c773ac
9 changed files with 115 additions and 115 deletions
Download Patch File Download Diff File Expand all files Collapse all files

200
drivers/gpu/nvgpu/common/power_features/cg/cg.c
View File

@@ -169,11 +169,11 @@ void nvgpu_cg_blcg_fb_ltc_load_enable(struct gk20a *g)
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.clock_gating.blcg_fb_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_fb_load_gating_prod(g, true);
if (g->ops.cg.blcg_fb_load_gating_prod != NULL) {
g->ops.cg.blcg_fb_load_gating_prod(g, true);
}
if (g->ops.clock_gating.blcg_ltc_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_ltc_load_gating_prod(g, true);
if (g->ops.cg.blcg_ltc_load_gating_prod != NULL) {
g->ops.cg.blcg_ltc_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -191,8 +191,8 @@ void nvgpu_cg_blcg_fifo_load_enable(struct gk20a *g)
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.clock_gating.blcg_fifo_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_fifo_load_gating_prod(g, true);
if (g->ops.cg.blcg_fifo_load_gating_prod != NULL) {
g->ops.cg.blcg_fifo_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -210,8 +210,8 @@ void nvgpu_cg_blcg_pmu_load_enable(struct gk20a *g)
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.clock_gating.blcg_pmu_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_pmu_load_gating_prod(g, true);
if (g->ops.cg.blcg_pmu_load_gating_prod != NULL) {
g->ops.cg.blcg_pmu_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -229,8 +229,8 @@ void nvgpu_cg_blcg_ce_load_enable(struct gk20a *g)
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.clock_gating.blcg_ce_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_ce_load_gating_prod(g, true);
if (g->ops.cg.blcg_ce_load_gating_prod != NULL) {
g->ops.cg.blcg_ce_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -248,8 +248,8 @@ void nvgpu_cg_blcg_gr_load_enable(struct gk20a *g)
if (!g->blcg_enabled) {
goto done;
}
if (g->ops.clock_gating.blcg_gr_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_gr_load_gating_prod(g, true);
if (g->ops.cg.blcg_gr_load_gating_prod != NULL) {
g->ops.cg.blcg_gr_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -267,11 +267,11 @@ void nvgpu_cg_slcg_fb_ltc_load_enable(struct gk20a *g)
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.clock_gating.slcg_fb_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_fb_load_gating_prod(g, true);
if (g->ops.cg.slcg_fb_load_gating_prod != NULL) {
g->ops.cg.slcg_fb_load_gating_prod(g, true);
}
if (g->ops.clock_gating.slcg_ltc_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_ltc_load_gating_prod(g, true);
if (g->ops.cg.slcg_ltc_load_gating_prod != NULL) {
g->ops.cg.slcg_ltc_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -289,8 +289,8 @@ void nvgpu_cg_slcg_priring_load_enable(struct gk20a *g)
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.clock_gating.slcg_priring_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_priring_load_gating_prod(g, true);
if (g->ops.cg.slcg_priring_load_gating_prod != NULL) {
g->ops.cg.slcg_priring_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -310,14 +310,14 @@ void nvgpu_cg_slcg_gr_perf_ltc_load_enable(struct gk20a *g)
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.clock_gating.slcg_ltc_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_ltc_load_gating_prod(g, true);
if (g->ops.cg.slcg_ltc_load_gating_prod != NULL) {
g->ops.cg.slcg_ltc_load_gating_prod(g, true);
}
if (g->ops.clock_gating.slcg_perf_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_perf_load_gating_prod(g, true);
if (g->ops.cg.slcg_perf_load_gating_prod != NULL) {
g->ops.cg.slcg_perf_load_gating_prod(g, true);
}
if (g->ops.clock_gating.slcg_gr_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_gr_load_gating_prod(g, true);
if (g->ops.cg.slcg_gr_load_gating_prod != NULL) {
g->ops.cg.slcg_gr_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -337,14 +337,14 @@ void nvgpu_cg_slcg_gr_perf_ltc_load_disable(struct gk20a *g)
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.clock_gating.slcg_gr_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_gr_load_gating_prod(g, false);
if (g->ops.cg.slcg_gr_load_gating_prod != NULL) {
g->ops.cg.slcg_gr_load_gating_prod(g, false);
}
if (g->ops.clock_gating.slcg_perf_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_perf_load_gating_prod(g, false);
if (g->ops.cg.slcg_perf_load_gating_prod != NULL) {
g->ops.cg.slcg_perf_load_gating_prod(g, false);
}
if (g->ops.clock_gating.slcg_ltc_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_ltc_load_gating_prod(g, false);
if (g->ops.cg.slcg_ltc_load_gating_prod != NULL) {
g->ops.cg.slcg_ltc_load_gating_prod(g, false);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -361,8 +361,8 @@ void nvgpu_cg_slcg_fifo_load_enable(struct gk20a *g)
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.clock_gating.slcg_fifo_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_fifo_load_gating_prod(g, true);
if (g->ops.cg.slcg_fifo_load_gating_prod != NULL) {
g->ops.cg.slcg_fifo_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -380,8 +380,8 @@ void nvgpu_cg_slcg_pmu_load_enable(struct gk20a *g)
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.clock_gating.slcg_pmu_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_pmu_load_gating_prod(g, true);
if (g->ops.cg.slcg_pmu_load_gating_prod != NULL) {
g->ops.cg.slcg_pmu_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -399,8 +399,8 @@ void nvgpu_cg_slcg_ce2_load_enable(struct gk20a *g)
if (!g->slcg_enabled) {
goto done;
}
if (g->ops.clock_gating.slcg_ce2_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_ce2_load_gating_prod(g, true);
if (g->ops.cg.slcg_ce2_load_gating_prod != NULL) {
g->ops.cg.slcg_ce2_load_gating_prod(g, true);
}
done:
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -419,24 +419,24 @@ void nvgpu_cg_init_gr_load_gating_prod(struct gk20a *g)
goto check_can_blcg;
}
if (g->ops.clock_gating.slcg_bus_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_bus_load_gating_prod(g, true);
if (g->ops.cg.slcg_bus_load_gating_prod != NULL) {
g->ops.cg.slcg_bus_load_gating_prod(g, true);
}
if (g->ops.clock_gating.slcg_chiplet_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_chiplet_load_gating_prod(g, true);
if (g->ops.cg.slcg_chiplet_load_gating_prod != NULL) {
g->ops.cg.slcg_chiplet_load_gating_prod(g, true);
}
if (g->ops.clock_gating.slcg_gr_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_gr_load_gating_prod(g, true);
if (g->ops.cg.slcg_gr_load_gating_prod != NULL) {
g->ops.cg.slcg_gr_load_gating_prod(g, true);
}
if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g,
if (g->ops.cg.slcg_ctxsw_firmware_load_gating_prod != NULL) {
g->ops.cg.slcg_ctxsw_firmware_load_gating_prod(g,
true);
}
if (g->ops.clock_gating.slcg_perf_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_perf_load_gating_prod(g, true);
if (g->ops.cg.slcg_perf_load_gating_prod != NULL) {
g->ops.cg.slcg_perf_load_gating_prod(g, true);
}
if (g->ops.clock_gating.slcg_xbar_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_xbar_load_gating_prod(g, true);
if (g->ops.cg.slcg_xbar_load_gating_prod != NULL) {
g->ops.cg.slcg_xbar_load_gating_prod(g, true);
}
check_can_blcg:
@@ -446,22 +446,22 @@ check_can_blcg:
if (!g->blcg_enabled) {
goto pg_gr_load;
}
if (g->ops.clock_gating.blcg_bus_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_bus_load_gating_prod(g, true);
if (g->ops.cg.blcg_bus_load_gating_prod != NULL) {
g->ops.cg.blcg_bus_load_gating_prod(g, true);
}
if (g->ops.clock_gating.blcg_gr_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_gr_load_gating_prod(g, true);
if (g->ops.cg.blcg_gr_load_gating_prod != NULL) {
g->ops.cg.blcg_gr_load_gating_prod(g, true);
}
if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g,
if (g->ops.cg.blcg_ctxsw_firmware_load_gating_prod != NULL) {
g->ops.cg.blcg_ctxsw_firmware_load_gating_prod(g,
true);
}
if (g->ops.clock_gating.blcg_xbar_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_xbar_load_gating_prod(g, true);
if (g->ops.cg.blcg_xbar_load_gating_prod != NULL) {
g->ops.cg.blcg_xbar_load_gating_prod(g, true);
}
pg_gr_load:
if (g->ops.clock_gating.pg_gr_load_gating_prod != NULL) {
g->ops.clock_gating.pg_gr_load_gating_prod(g, true);
if (g->ops.cg.pg_gr_load_gating_prod != NULL) {
g->ops.cg.pg_gr_load_gating_prod(g, true);
}
nvgpu_mutex_release(&g->cg_pg_lock);
@@ -520,33 +520,33 @@ void nvgpu_cg_blcg_set_blcg_enabled(struct gk20a *g, bool enable)
goto done;
}
if (g->ops.clock_gating.blcg_bus_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_bus_load_gating_prod(g, enable);
if (g->ops.cg.blcg_bus_load_gating_prod != NULL) {
g->ops.cg.blcg_bus_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.blcg_ce_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_ce_load_gating_prod(g, enable);
if (g->ops.cg.blcg_ce_load_gating_prod != NULL) {
g->ops.cg.blcg_ce_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g,
if (g->ops.cg.blcg_ctxsw_firmware_load_gating_prod != NULL) {
g->ops.cg.blcg_ctxsw_firmware_load_gating_prod(g,
enable);
}
if (g->ops.clock_gating.blcg_fb_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_fb_load_gating_prod(g, enable);
if (g->ops.cg.blcg_fb_load_gating_prod != NULL) {
g->ops.cg.blcg_fb_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.blcg_fifo_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_fifo_load_gating_prod(g, enable);
if (g->ops.cg.blcg_fifo_load_gating_prod != NULL) {
g->ops.cg.blcg_fifo_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.blcg_gr_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_gr_load_gating_prod(g, enable);
if (g->ops.cg.blcg_gr_load_gating_prod != NULL) {
g->ops.cg.blcg_gr_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.blcg_ltc_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_ltc_load_gating_prod(g, enable);
if (g->ops.cg.blcg_ltc_load_gating_prod != NULL) {
g->ops.cg.blcg_ltc_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.blcg_pmu_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_pmu_load_gating_prod(g, enable);
if (g->ops.cg.blcg_pmu_load_gating_prod != NULL) {
g->ops.cg.blcg_pmu_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.blcg_xbar_load_gating_prod != NULL) {
g->ops.clock_gating.blcg_xbar_load_gating_prod(g, enable);
if (g->ops.cg.blcg_xbar_load_gating_prod != NULL) {
g->ops.cg.blcg_xbar_load_gating_prod(g, enable);
}
done:
@@ -581,44 +581,44 @@ void nvgpu_cg_slcg_set_slcg_enabled(struct gk20a *g, bool enable)
goto done;
}
if (g->ops.clock_gating.slcg_bus_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_bus_load_gating_prod(g, enable);
if (g->ops.cg.slcg_bus_load_gating_prod != NULL) {
g->ops.cg.slcg_bus_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.slcg_ce2_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_ce2_load_gating_prod(g, enable);
if (g->ops.cg.slcg_ce2_load_gating_prod != NULL) {
g->ops.cg.slcg_ce2_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.slcg_chiplet_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_chiplet_load_gating_prod(g, enable);
if (g->ops.cg.slcg_chiplet_load_gating_prod != NULL) {
g->ops.cg.slcg_chiplet_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod !=
if (g->ops.cg.slcg_ctxsw_firmware_load_gating_prod !=
NULL) {
g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g,
g->ops.cg.slcg_ctxsw_firmware_load_gating_prod(g,
enable);
}
if (g->ops.clock_gating.slcg_fb_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_fb_load_gating_prod(g, enable);
if (g->ops.cg.slcg_fb_load_gating_prod != NULL) {
g->ops.cg.slcg_fb_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.slcg_fifo_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_fifo_load_gating_prod(g, enable);
if (g->ops.cg.slcg_fifo_load_gating_prod != NULL) {
g->ops.cg.slcg_fifo_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.slcg_gr_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_gr_load_gating_prod(g, enable);
if (g->ops.cg.slcg_gr_load_gating_prod != NULL) {
g->ops.cg.slcg_gr_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.slcg_ltc_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_ltc_load_gating_prod(g, enable);
if (g->ops.cg.slcg_ltc_load_gating_prod != NULL) {
g->ops.cg.slcg_ltc_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.slcg_perf_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_perf_load_gating_prod(g, enable);
if (g->ops.cg.slcg_perf_load_gating_prod != NULL) {
g->ops.cg.slcg_perf_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.slcg_priring_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_priring_load_gating_prod(g,
if (g->ops.cg.slcg_priring_load_gating_prod != NULL) {
g->ops.cg.slcg_priring_load_gating_prod(g,
enable);
}
if (g->ops.clock_gating.slcg_pmu_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_pmu_load_gating_prod(g, enable);
if (g->ops.cg.slcg_pmu_load_gating_prod != NULL) {
g->ops.cg.slcg_pmu_load_gating_prod(g, enable);
}
if (g->ops.clock_gating.slcg_xbar_load_gating_prod != NULL) {
g->ops.clock_gating.slcg_xbar_load_gating_prod(g, enable);
if (g->ops.cg.slcg_xbar_load_gating_prod != NULL) {
g->ops.cg.slcg_xbar_load_gating_prod(g, enable);
}
done:

4
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -374,7 +374,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.set_debug_mode = vgpu_mm_mmu_set_debug_mode,
.tlb_invalidate = vgpu_mm_tlb_invalidate,
},
.clock_gating = {
.cg = {
.slcg_bus_load_gating_prod = NULL,
.slcg_ce2_load_gating_prod = NULL,
.slcg_chiplet_load_gating_prod = NULL,
@@ -728,7 +728,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
gops->gr.config = vgpu_gp10b_ops.gr.config;
gops->fb = vgpu_gp10b_ops.fb;
gops->perf = vgpu_gp10b_ops.perf;
gops->clock_gating = vgpu_gp10b_ops.clock_gating;
gops->cg = vgpu_gp10b_ops.cg;
gops->fifo = vgpu_gp10b_ops.fifo;
gops->engine = vgpu_gp10b_ops.engine;
gops->pbdma = vgpu_gp10b_ops.pbdma;

4
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -445,7 +445,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.read_mmu_fault_info = fb_gv11b_read_mmu_fault_info,
.read_mmu_fault_status = fb_gv11b_read_mmu_fault_status,
},
.clock_gating = {
.cg = {
.slcg_bus_load_gating_prod = NULL,
.slcg_ce2_load_gating_prod = NULL,
.slcg_chiplet_load_gating_prod = NULL,
@@ -810,7 +810,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
gops->gr.config = vgpu_gv11b_ops.gr.config;
gops->fb = vgpu_gv11b_ops.fb;
gops->perf = vgpu_gv11b_ops.perf;
gops->clock_gating = vgpu_gv11b_ops.clock_gating;
gops->cg = vgpu_gv11b_ops.cg;
gops->fifo = vgpu_gv11b_ops.fifo;
gops->engine = vgpu_gv11b_ops.engine;
gops->pbdma = vgpu_gv11b_ops.pbdma;

4
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -506,7 +506,7 @@ static const struct gpu_ops gm20b_ops = {
.tlb_invalidate = gm20b_fb_tlb_invalidate,
.mem_unlock = NULL,
},
.clock_gating = {
.cg = {
.slcg_bus_load_gating_prod =
gm20b_slcg_bus_load_gating_prod,
.slcg_ce2_load_gating_prod =
@@ -940,7 +940,7 @@ int gm20b_init_hal(struct gk20a *g)
gops->gr.ctxsw_prog = gm20b_ops.gr.ctxsw_prog;
gops->gr.config = gm20b_ops.gr.config;
gops->fb = gm20b_ops.fb;
gops->clock_gating = gm20b_ops.clock_gating;
gops->cg = gm20b_ops.cg;
gops->fifo = gm20b_ops.fifo;
gops->engine = gm20b_ops.engine;
gops->pbdma = gm20b_ops.pbdma;

4
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -583,7 +583,7 @@ static const struct gpu_ops gp10b_ops = {
.tlb_invalidate = gm20b_fb_tlb_invalidate,
.mem_unlock = NULL,
},
.clock_gating = {
.cg = {
.slcg_bus_load_gating_prod =
gp10b_slcg_bus_load_gating_prod,
.slcg_ce2_load_gating_prod =
@@ -1028,7 +1028,7 @@ int gp10b_init_hal(struct gk20a *g)
gops->gr.ctxsw_prog = gp10b_ops.gr.ctxsw_prog;
gops->gr.config = gp10b_ops.gr.config;
gops->fb = gp10b_ops.fb;
gops->clock_gating = gp10b_ops.clock_gating;
gops->cg = gp10b_ops.cg;
gops->fifo = gp10b_ops.fifo;
gops->engine = gp10b_ops.engine;
gops->pbdma = gp10b_ops.pbdma;

4
drivers/gpu/nvgpu/gv100/hal_gv100.c
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@@ -757,7 +757,7 @@ static const struct gpu_ops gv100_ops = {
.nvdec = {
.falcon_base_addr = gp106_nvdec_falcon_base_addr,
},
.clock_gating = {
.cg = {
.slcg_bus_load_gating_prod =
gv100_slcg_bus_load_gating_prod,
.slcg_ce2_load_gating_prod =
@@ -1322,7 +1322,7 @@ int gv100_init_hal(struct gk20a *g)
gops->gr.config = gv100_ops.gr.config;
gops->fb = gv100_ops.fb;
gops->nvdec = gv100_ops.nvdec;
gops->clock_gating = gv100_ops.clock_gating;
gops->cg = gv100_ops.cg;
gops->fifo = gv100_ops.fifo;
gops->engine = gv100_ops.engine;
gops->pbdma = gv100_ops.pbdma;

4
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
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@@ -713,7 +713,7 @@ static const struct gpu_ops gv11b_ops = {
.fault_buf_set_state_hw = gv11b_fb_fault_buf_set_state_hw,
.fault_buf_configure_hw = gv11b_fb_fault_buf_configure_hw,
},
.clock_gating = {
.cg = {
.slcg_bus_load_gating_prod =
gv11b_slcg_bus_load_gating_prod,
.slcg_ce2_load_gating_prod =
@@ -1193,7 +1193,7 @@ int gv11b_init_hal(struct gk20a *g)
gops->gr.ctxsw_prog = gv11b_ops.gr.ctxsw_prog;
gops->gr.config = gv11b_ops.gr.config;
gops->fb = gv11b_ops.fb;
gops->clock_gating = gv11b_ops.clock_gating;
gops->cg = gv11b_ops.cg;
gops->fifo = gv11b_ops.fifo;
gops->engine = gv11b_ops.engine;
gops->pbdma = gv11b_ops.pbdma;

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
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@@ -866,7 +866,7 @@ struct gpu_ops {
void (*blcg_pmu_load_gating_prod)(struct gk20a *g, bool prod);
void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod);
void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod);
} clock_gating;
} cg;
struct {
int (*setup_sw)(struct gk20a *g);
void (*cleanup_sw)(struct gk20a *g);

4
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -794,7 +794,7 @@ static const struct gpu_ops tu104_ops = {
.nvdec = {
.falcon_base_addr = tu104_nvdec_falcon_base_addr,
},
.clock_gating = {
.cg = {
.slcg_bus_load_gating_prod =
tu104_slcg_bus_load_gating_prod,
.slcg_ce2_load_gating_prod =
@@ -1365,7 +1365,7 @@ int tu104_init_hal(struct gk20a *g)
gops->gr.config = tu104_ops.gr.config;
gops->fb = tu104_ops.fb;
gops->nvdec = tu104_ops.nvdec;
gops->clock_gating = tu104_ops.clock_gating;
gops->cg = tu104_ops.cg;
gops->fifo = tu104_ops.fifo;
gops->engine = tu104_ops.engine;
gops->pbdma = tu104_ops.pbdma;