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Revert "gpu: nvgpu: add turing support"
This reverts commit 27686d8b56316c7ad772dd91548e91516d59f3b1. Change-Id: Iebda705858edbd58c10ca3024a4ad060401485b6 Signed-off-by: David Gilhooley <dgilhooley@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1918612
This commit is contained in:
David Gilhooley
committed by
Abdul Salam
Abdul Salam
parent
51244d6112
commit
b74a4dbd26
@@ -1,283 +0,0 @@
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/dma.h>
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#include <nvgpu/types.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/log2.h>
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#include <nvgpu/channel.h>
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#include "gk20a/gk20a.h"
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#include "gk20a/fifo_gk20a.h"
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#include "gp10b/fifo_gp10b.h"
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#include "gv11b/fifo_gv11b.h"
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#include "tu104/fifo_tu104.h"
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#include "tu104/func_tu104.h"
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#include <nvgpu/hw/tu104/hw_fifo_tu104.h>
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#include <nvgpu/hw/tu104/hw_pbdma_tu104.h>
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#include <nvgpu/hw/tu104/hw_ram_tu104.h>
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#include <nvgpu/hw/tu104/hw_func_tu104.h>
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#include <nvgpu/hw/tu104/hw_ctrl_tu104.h>
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int channel_tu104_setup_ramfc(struct channel_gk20a *c,
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u64 gpfifo_base, u32 gpfifo_entries,
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unsigned long acquire_timeout, u32 flags)
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{
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struct gk20a *g = c->g;
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struct nvgpu_mem *mem = &c->inst_block;
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u32 data;
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nvgpu_log_fn(g, " ");
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nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v());
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nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
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pbdma_gp_base_offset_f(
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u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
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nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
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pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
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pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
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nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
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c->g->ops.fifo.get_pbdma_signature(c->g));
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nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
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pbdma_pb_header_method_zero_f() |
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pbdma_pb_header_subchannel_zero_f() |
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pbdma_pb_header_level_main_f() |
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pbdma_pb_header_first_true_f() |
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pbdma_pb_header_type_inc_f());
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nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(),
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pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) |
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pbdma_subdevice_status_active_f() |
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pbdma_subdevice_channel_dma_enable_f());
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nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
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pbdma_target_eng_ctx_valid_true_f() |
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pbdma_target_ce_ctx_valid_true_f() |
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pbdma_target_engine_sw_f());
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nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
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g->ops.fifo.pbdma_acquire_val(acquire_timeout));
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nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
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pbdma_set_channel_info_veid_f(c->subctx_id));
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nvgpu_mem_wr32(g, mem, ram_in_engine_wfi_veid_w(),
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ram_in_engine_wfi_veid_f(c->subctx_id));
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gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem);
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if (c->is_privileged_channel) {
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/* Set privilege level for channel */
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nvgpu_mem_wr32(g, mem, ram_fc_config_w(),
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pbdma_config_auth_level_privileged_f());
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gk20a_fifo_setup_ramfc_for_privileged_channel(c);
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}
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/* Enable userd writeback */
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data = nvgpu_mem_rd32(g, mem, ram_fc_config_w());
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data = data | pbdma_config_userd_writeback_enable_f();
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nvgpu_mem_wr32(g, mem, ram_fc_config_w(),data);
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gv11b_userd_writeback_config(g);
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return channel_gp10b_commit_userd(c);
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}
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void tu104_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
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u32 count, u32 buffer_index)
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{
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struct fifo_runlist_info_gk20a *runlist = NULL;
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u64 runlist_iova;
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u32 runlist_iova_lo, runlist_iova_hi;
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runlist = &g->fifo.runlist_info[runlist_id];
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runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]);
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runlist_iova_lo = u64_lo32(runlist_iova) >>
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fifo_runlist_base_lo_ptr_align_shift_v();
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runlist_iova_hi = u64_hi32(runlist_iova);
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if (count != 0) {
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nvgpu_writel(g, fifo_runlist_base_lo_r(runlist_id),
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fifo_runlist_base_lo_ptr_lo_f(runlist_iova_lo) |
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nvgpu_aperture_mask(g, &runlist->mem[buffer_index],
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fifo_runlist_base_lo_target_sys_mem_ncoh_f(),
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fifo_runlist_base_lo_target_sys_mem_coh_f(),
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fifo_runlist_base_lo_target_vid_mem_f()));
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nvgpu_writel(g, fifo_runlist_base_hi_r(runlist_id),
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fifo_runlist_base_hi_ptr_hi_f(runlist_iova_hi));
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}
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nvgpu_writel(g, fifo_runlist_submit_r(runlist_id),
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fifo_runlist_submit_length_f(count));
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}
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int tu104_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
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{
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struct nvgpu_timeout timeout;
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unsigned long delay = GR_IDLE_CHECK_DEFAULT;
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int ret = -ETIMEDOUT;
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ret = nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
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NVGPU_TIMER_CPU_TIMER);
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if (ret != 0) {
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return ret;
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}
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ret = -ETIMEDOUT;
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do {
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if ((nvgpu_readl(g, fifo_runlist_submit_info_r(runlist_id)) &
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fifo_runlist_submit_info_pending_true_f()) == 0) {
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ret = 0;
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break;
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}
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nvgpu_usleep_range(delay, delay * 2);
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delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
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} while (!nvgpu_timeout_expired(&timeout));
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return ret;
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}
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int tu104_init_fifo_setup_hw(struct gk20a *g)
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{
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u32 val;
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nvgpu_log_fn(g, " ");
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/*
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* Required settings for tu104_ring_channel_doorbell()
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*/
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val = nvgpu_readl(g, ctrl_virtual_channel_cfg_r(0));
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val |= ctrl_virtual_channel_cfg_pending_enable_true_f();
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nvgpu_writel(g, ctrl_virtual_channel_cfg_r(0), val);
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return gv11b_init_fifo_setup_hw(g);
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}
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void tu104_ring_channel_doorbell(struct channel_gk20a *c)
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{
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struct fifo_gk20a *f = &c->g->fifo;
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u32 hw_chid = f->channel_base + c->chid;
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nvgpu_log_info(c->g, "channel ring door bell %d, runlist %d",
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c->chid, c->runlist_id);
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nvgpu_func_writel(c->g, func_doorbell_r(),
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ctrl_doorbell_vector_f(hw_chid) |
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ctrl_doorbell_runlist_id_f(c->runlist_id));
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}
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int tu104_init_pdb_cache_war(struct gk20a *g)
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{
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u32 size = PAGE_SIZE * 258U;
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u64 last_bind_pdb_addr;
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u64 pdb_addr;
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u32 pdb_addr_lo, pdb_addr_hi;
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u32 i;
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int err;
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if (nvgpu_mem_is_valid(&g->pdb_cache_war_mem)) {
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return 0;
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}
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/*
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* Allocate memory for 257 instance block binds +
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* PDB bound to 257th instance block
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*/
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err = nvgpu_dma_alloc_sys(g, size, &g->pdb_cache_war_mem);
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if (err) {
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return err;
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}
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/*
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* 257th instance block (i.e. last bind) needs to be bound to
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* valid memory
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* First 256 binds can happen to dummy addresses
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*/
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pdb_addr = PAGE_SIZE;
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last_bind_pdb_addr = nvgpu_mem_get_addr(g, &g->pdb_cache_war_mem) +
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(257U * PAGE_SIZE);
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/* Setup first 256 instance blocks */
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for (i = 0U; i < 256U; i++) {
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pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
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pdb_addr_hi = u64_hi32(pdb_addr);
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nvgpu_mem_wr32(g, &g->pdb_cache_war_mem,
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ram_in_page_dir_base_lo_w() + (i * PAGE_SIZE / 4),
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nvgpu_aperture_mask(g, &g->pdb_cache_war_mem,
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ram_in_page_dir_base_target_sys_mem_ncoh_f(),
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ram_in_page_dir_base_target_sys_mem_coh_f(),
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ram_in_page_dir_base_target_vid_mem_f()) |
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ram_in_page_dir_base_vol_true_f() |
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ram_in_big_page_size_64kb_f() |
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ram_in_page_dir_base_lo_f(pdb_addr_lo) |
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ram_in_use_ver2_pt_format_true_f());
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nvgpu_mem_wr32(g, &g->pdb_cache_war_mem,
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ram_in_page_dir_base_hi_w() + (i * PAGE_SIZE / 4),
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ram_in_page_dir_base_hi_f(pdb_addr_hi));
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pdb_addr += PAGE_SIZE;
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}
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/* Setup 257th instance block */
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pdb_addr_lo = u64_lo32(last_bind_pdb_addr >> ram_in_base_shift_v());
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pdb_addr_hi = u64_hi32(last_bind_pdb_addr);
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nvgpu_mem_wr32(g, &g->pdb_cache_war_mem,
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ram_in_page_dir_base_lo_w() + (256U * PAGE_SIZE / 4),
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nvgpu_aperture_mask(g, &g->pdb_cache_war_mem,
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ram_in_page_dir_base_target_sys_mem_ncoh_f(),
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ram_in_page_dir_base_target_sys_mem_coh_f(),
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ram_in_page_dir_base_target_vid_mem_f()) |
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ram_in_page_dir_base_vol_true_f() |
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ram_in_big_page_size_64kb_f() |
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ram_in_page_dir_base_lo_f(pdb_addr_lo) |
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ram_in_use_ver2_pt_format_true_f());
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nvgpu_mem_wr32(g, &g->pdb_cache_war_mem,
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ram_in_page_dir_base_hi_w() + (256U * PAGE_SIZE / 4),
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ram_in_page_dir_base_hi_f(pdb_addr_hi));
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return 0;
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}
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void tu104_deinit_pdb_cache_war(struct gk20a *g)
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{
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if (nvgpu_mem_is_valid(&g->pdb_cache_war_mem)) {
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nvgpu_dma_free(g, &g->pdb_cache_war_mem);
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}
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}
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