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gpu: nvgpu: Disable rd_coalesce for all chips

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Disable read coalescing for all chips.

Bug 200314091

Change-Id: Iaa3f58f94369ae1edae0620083eca4594be730fd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1518308
Signed-off-by: Darren Sun <darrens@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1551739
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hayden Du <haydend@nvidia.com>
This commit is contained in:
Darren Sun
2017-09-05 16:01:13 +08:00
committed by mobile promotions
parent 5ecd220d32
commit b79a75517a
3 changed files with 21 additions and 0 deletions
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1
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -351,6 +351,7 @@ struct gpu_ops {
void (*load_tpc_mask)(struct gk20a *g);
int (*set_czf_bypass)(struct gk20a *g,
struct channel_gk20a *ch);
void (*disable_rd_coalesce)(struct gk20a *g);
} gr;
const char *name;
struct {

3
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -4822,6 +4822,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
if (g->ops.ltc.init_cbc)
g->ops.ltc.init_cbc(g, gr);
if (g->ops.gr.disable_rd_coalesce)
g->ops.gr.disable_rd_coalesce(g);
/* load ctx init */
for (i = 0; i < sw_ctx_load->count; i++)
gk20a_writel(g, sw_ctx_load->l[i].addr,

17
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -1517,6 +1517,23 @@ static void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
priv_addr_table, priv_addr_table_index);
}
/*
* * Disable both surface and LG coalesce.
* */
void gm20a_gr_disable_rd_coalesce(struct gk20a *g)
{
u32 dbg2_reg;
dbg2_reg = gk20a_readl(g, gr_gpcs_tpcs_tex_m_dbg2_r());
dbg2_reg = set_field(dbg2_reg,
gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(),
gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(0));
dbg2_reg = set_field(dbg2_reg,
gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(),
gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(0));
gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), dbg2_reg);
}
void gm20b_init_gr(struct gpu_ops *gops)
{
gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu;