nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: add sm_debugger_attached gr ops

Browse Source 
This is required to support t19x sm register address changes

JIRA GPUT19X-75

Change-Id: I7f961147e0e6464a71e240487f7bc964b0544e5d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512213
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Seema Khowala
2017-07-02 11:21:24 -07:00
committed by mobile promotions
parent 3b1ab45ccc
commit b7ae37cc32
4 changed files with 7 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1268,7 +1268,7 @@ bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,
/* channel recovery is only deferred if an sm debugger
is attached and has MMU debug mode is enabled */
if (!gk20a_gr_sm_debugger_attached(g) ||
if (!g->ops.gr.sm_debugger_attached(g) ||
!g->ops.fb.is_debug_mode_enabled(g))
return false;

1
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -369,6 +369,7 @@ struct gpu_ops {
u32 (*tpc_enabled_exceptions)(struct gk20a *g);
int (*set_czf_bypass)(struct gk20a *g,
struct channel_gk20a *ch);
bool (*sm_debugger_attached)(struct gk20a *g);
} gr;
struct {
void (*init_hw)(struct gk20a *g);

8
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -5543,7 +5543,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() |
gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f();
u32 global_esr, warp_esr;
bool sm_debugger_attached = gk20a_gr_sm_debugger_attached(g);
bool sm_debugger_attached = g->ops.gr.sm_debugger_attached(g);
gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "");
@@ -5978,7 +5978,7 @@ int gk20a_gr_isr(struct gk20a *g)
&post_event, fault_ch, &global_esr);
/* signal clients waiting on an event */
if (gk20a_gr_sm_debugger_attached(g) &&
if (g->ops.gr.sm_debugger_attached(g) &&
post_event && fault_ch) {
gk20a_dbg_gpu_post_events(fault_ch);
}
@@ -8025,7 +8025,7 @@ void gk20a_suspend_single_sm(struct gk20a *g,
offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
/* if an SM debugger isn't attached, skip suspend */
if (!gk20a_gr_sm_debugger_attached(g)) {
if (!g->ops.gr.sm_debugger_attached(g)) {
nvgpu_err(g,
"SM debugger not attached, skipping suspend!");
return;
@@ -8056,7 +8056,7 @@ void gk20a_suspend_all_sms(struct gk20a *g,
u32 dbgr_control0;
/* if an SM debugger isn't attached, skip suspend */
if (!gk20a_gr_sm_debugger_attached(g)) {
if (!g->ops.gr.sm_debugger_attached(g)) {
nvgpu_err(g,
"SM debugger not attached, skipping suspend!");
return;

1
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -1630,4 +1630,5 @@ void gm20b_init_gr(struct gpu_ops *gops)
gops->gr.clear_sm_errors = gr_gk20a_clear_sm_errors;
gops->gr.tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions;
gops->gr.get_esr_sm_sel = gk20a_gr_get_esr_sm_sel;
gops->gr.sm_debugger_attached = gk20a_gr_sm_debugger_attached;
}