nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: add hal for fecs ctsw clear mailbox

Browse Source 
Add hal to have chip specific fecs ctxsw mailbox clear function.
This hal has following prototype with mailbox reg_index and bitmask
for clear_val:
void (*fecs_ctxsw_clear_mailbox)(struct gk20a *g,
			u32 reg_index, u32  clear_val);

JIRA NVGPU-4870

Change-Id: I1d20309224f856872dc97040ecf7628c60fb2802
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287921
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2020-01-30 14:03:37 -08:00
committed by Alex Waterman
parent b57bd925f9
commit b811a0b755
8 changed files with 36 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
View File

@@ -253,6 +253,19 @@ struct gops_gr_falcon {
u32 (*read_fecs_ctxsw_mailbox)(struct gk20a *g,
u32 reg_index);
/**
* @brief Clear context switch mailbox for bitmask speciifed.
*
* @param g [in] Pointer to GPU driver struct.
* @param reg_index [in] Register Index value.
* clear_val [in] Bitmask of bits to be clear.
*
* This function clears specified bitmask of context switch mailbox
* register value.
*/
void (*fecs_ctxsw_clear_mailbox)(struct gk20a *g,
u32 reg_index, u32 clear_val);
/**
* @brief Dump context switch mailbox register values.
*